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ksz8993m/ml integrated 3-port 10/100 managed switch with phys rev 1.06 micrel inc. 2180 fortune drive san jose, ca 95131 usa tel +1 ( 408 ) 944-0800 fax + 1 (408) 474-1000 http://www.micrel.com october 2008 1 m9999-020606 general description the ksz8993m, a highly integrated layer 2 managed switch, is designed for low port count, cost-sensitive 10/100 mbps switch systems. it offers an extensive feature set that includes tag/port-based vlan, quality of service (qos) priority, management, management information base (mib) counters, mii/sni, and cpu c ontrol/data interfaces to effectively address both current and emerging fast ethernet applications. the ksz8993m contains two 10/100 transceivers with patented mixed-signal low-power technology, three media access control (mac) units, a high- speed non-blocking switch fabric, a dedicated address lookup engine, and an on-chip frame buffer memory. both phy units support 10base-t and 100base- tx. in addition, one of the phy unit supports 100base-fx. the ksz8993ml is the single supply version with all the identical rich features of the ksz8993m. ___________________________________________________________________________________________________ functional diagram downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 2 m9999-020606 1klook-up engine queue manageme nt bu f f er manageme nt frame buffers mib co u n t e r s eep rom interface fif o, fl o w co n t r o l , vlantagging,priority 10/100 mac1 10/100 mac2 10/100 mac3 10/100 t/tx/fx phy 1 10/100 t/tx phy 2 sni spi co n t r o l registers strap-in configuration pins led drivers auto mdi/mdi-x auto mdi/mdi-x mii/sni spi miim smi i 2 c p1 led[3:0]p2 led[3:0] features proven integrated 3-port 10/100 ethernet switch C 2nd generation switch with three macs and two phys fully compliant to ieee 802.3u standard C non-blocking switch fabric assures fast packet delivery by utilizing a 1k mac address lookup table and a store-and-forward architecture C full duplex ieee 802.3x flow control (pause) with force mode option C half-duplex back pressure flow control C automatic mdi/mdi-x crossover with disable and enable option C 100base-fx support on port 1 C mii interface supports both mac mode and phy mode C 7-wire serial network interface (sni) support for legacy mac C comprehensive led indicator support for link, activity, full/half duplex and 10/100 speed comprehensive configuration register access C serial management interface (smi) to all internal registers C mii management (miim) interface to phy registers C spi and i 2 c interface to all internal registers C i/0 pins strapping and eeprom to program selective registers in unmanaged switch mode C control registers configurable on the fly (port- priority, 802.1p/d/q, an) qos/cos packet prioritization support C per port, 802.1p and diffserv-based C re-mapping of 802.1p priority field per port basis advanced switch features C ieee 802.1q vlan support for up to 16 groups (full-range of vlan id) C vlan id tag/untag options, per port basis C ieee 802.1p/q tag insertion or removal on a per port basis (egress) C programmable rate limiting from 0mbps to 100mbps at the ingress and egress port, rate options for high and low priority per port basis C broadcast storm protection with % control (global and per port basis) C ieee 802.1d spanning tree protocol support C upstream special tagging mode to inform the processor which ingress port receives the packet C igmp v1/v2 snooping support for multicast packet filtering C double-tagging support downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 3 m9999-020606 switch management features C port mirroring/monitoring/sniffing: ingress and/or egress traffic to any port or mii C mib counters for fully compliant statistics gathering, 34 mib counters per port C loopback modes for remote diagnostic of failure low power dissipation : <0.8 watts (includes phy transmit drivers) C full-chip hardware power-down (register configuration not saved) C per port based software power-save on phy (idle link detection, register configuration preserved) C 0.18um cmos technology C voltages: core 1.8v i/o and transceiver 3.3v use k8993ml for 3.3v only operation available in128-pin pqfp applications universal solutions C broadband gateway / firewall / vpn C integrated dsl or cable modem multi-port router C wireless lan access point + gateway C residential and enterprise voip gateway/phone C set-top/game box C home networking expansion C standalone 10/100 switch C fttx customer premises equipment C fiber broadband gateway upgradeable solutions (1) C unmanaged switch with future option to migrate to a managed solution C single phy alternative with future expansion option for two ports industrial solutions C applications requiring port redundancy and port monitoring C sensor devices in redundant ring topology note: 1. the cost and time of pcb re-spin. downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 4 m9999-020606 ordering information part number pb-free standard temperature range package ksz8993m ks8993m 0 o c to 70 o c 128-pin pqfp, lead-free ksz8993ml ks8993ml 0 o c to 70 o c 128-pin pqfp, lead-free ksz8993mi ks8993mi C40 o c to +85 o c 128-pin pqfp, lead-free ksz8993mli ks8993mli C40 o c to +85 o c 128-pin pqfp, lead-free downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 5 m9999-020606 revision history revision date summary of changes 1.00 5/14/03 created. 1.01 5/28/03 added ks8993mi availability in q4 2003. 1.02 12/8/03 changed v ddio , v ddatx and v ddarx supply voltages from 3.3v to (3.3v or 2.5v). changed [ps1,ps0] = [1,1] setting from reserved to smi mode. changed special tagging mode to upstream special tagging mode (switch port 3 to processor support only). updated recommended magnetic manufacturer list. added 25mhz crystal/oscillator clocks ppm spec. in pin description. updated i 2 c slave serial bus configuration section. updated ksz8993mi availability to from q1 2004. 1.03 9/22/04 added ks8993ml to general description (page 1) and to the functional description. updated part ordering information table. updated pin description for pin 22 to the following: v ddc : for ks8993m, this is an input power pin for the 1.8v digital core v dd . v out _1v8: for ks8993ml, this is an 1.8v output power pin to supply the ks8993mls input power pins: v ddap (pin 63), v ddc (pins 91, 123), and v dda (pins 38, 43, 57). updated pin description for p1led3 (pin 25) to indicate that an external 1k pull-down is needed if a led is connected. updated pin description for mdio (pin 95) to indicate that an external 4.7k pull-up is needed if this pin is in used. changed the aging period from 300 +/C75 seconds to about 200 seconds. updated electrical characteristics (v ih , v il , v oh , v ol ). transferred to new format. 1.04 4/12/05 removed references to 2.5v operation added reset circuit recommendation 1.05 2/14/05 updated to add pb-free spwcifications 1.06 2/13/07 add the p/n KSZ8993I into the ordering information table 1.06a 10/28/08 add the p/n ksz8993mli into the ordering information table modify the current consumption table from board to device. downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 6 m9999-020606 contents list of figures .........................................................................................................................................9 list of tables...........................................................................................................................................9 pin description and i/o assignment............................................................................................. ......10 pin configuration..................................................................................................................................20 functional description .........................................................................................................................21 functional overview: physical layer transceiver ............................................................................21 100base-tx transm it............................................................................................................ .............................................21 100base-tx recei ve ............................................................................................................. .............................................21 pll clock sy nthesi zer........................................................................................................................................................22 scrambler/de-scr ambler (100ba se-tx only) ....................................................................................... ............................22 100base-fx op eration.......................................................................................................................................................22 100base-fx signa l detection.................................................................................................... ........................................22 100base-fx far end fault....................................................................................................... ..........................................22 10base-t tr ansmit .............................................................................................................................................................23 10base-t recei ve ............................................................................................................... ...............................................23 power mana gement.............................................................................................................................................................23 mdi /mdi-x auto crosso ver...................................................................................................... ..........................................23 straight cable ................................................................................................................................................................ 23 crossover cable ................................................................................................................ ............................................25 auto negotiation ............................................................................................................... ..................................................25 functional overview: mac and switch ............................................................................................ ..27 address lookup ................................................................................................................. .................................................27 learning ...............................................................................................................................................................................27 migration ..............................................................................................................................................................................27 aging .......................................................................................................................... ..........................................................27 forwarding...........................................................................................................................................................................27 switching engine ............................................................................................................... .................................................30 mac operation .................................................................................................................. ..................................................30 inter packet gap (i pg) ......................................................................................................... .........................................30 back-off al gorit hm.........................................................................................................................................................30 late collis ion ................................................................................................................. ................................................30 illegal fram es ................................................................................................................................................................30 flow c ontrol...................................................................................................................................................................30 half-duplex backpre ssure .............................................................................................................................................30 broadcast storm protec tion ...........................................................................................................................................31 mii interface operation........................................................................................................................................................31 sni (7-wire) operation ........................................................................................................................................................32 mii management interface (miim) .......................................................................................................................................32 serial management interface (smi) ....................................................................................................................................33 advanced switch functions ...................................................................................................... ..........34 spanning tree support.......................................................................................................... .............................................34 upstream specia l tagging mode .................................................................................................. .....................................35 igmp support ................................................................................................................... ...................................................36 igmp sn ooping ...........................................................................................................................................................36 multicast address insertion in the static mac t able.......................................................................... .........................36 port mirroring support......................................................................................................... ...............................................36 ieee 802.1q vl an support ....................................................................................................... .........................................36 qos priority support........................................................................................................... ................................................37 rate limiti ng support .......................................................................................................... ...............................................39 configurati on inte rface ........................................................................................................ ...............................................39 i 2 c master serial bu s configur ation .............................................................................................. ................................39 i 2 c slave serial bus configur ation ............................................................................................... .................................40 spi slave serial bu s configur ation ............................................................................................. ..................................40 loopback s upport............................................................................................................... ................................................44 mii management (miim) registers ................................................................................................ .......45 downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 7 m9999-020606 register 0: mii basic co ntrol..........................................................................................................................................46 register 1: m ii basic status ...........................................................................................................................................46 register 2: phyid high ......................................................................................................... .......................................46 register 3: phyid low.......................................................................................................... .......................................46 register 4: auto-negotia tion advertisem ent ab ility ............................................................................. ...........................47 register 5: auto-negotiati on link partner ability .............................................................................. .............................47 register map: switch & phy (8 bit registers)................................................................................... ..48 global regi sters............................................................................................................... ..............................................48 port regi sters ................................................................................................................................................................48 advanced contro l regist ers...........................................................................................................................................48 global regi sters..................................................................................................................................................................48 register 0 (0x00): chip id0.................................................................................................... ........................................48 register 1 (0x01): chip id1 / start switch..................................................................................... .................................49 register 2 (0x02): global cont rol 0 ............................................................................................ ....................................49 register 3 (0x03): global cont rol 1 ............................................................................................ ....................................50 register 4 (0x04): global cont rol 2 ............................................................................................ ....................................50 register 5 (0x05): global cont rol 3 ............................................................................................ ....................................51 register 6 (0x06): global cont rol 4 ............................................................................................ ....................................52 register 7 (0x07): global cont rol 5 ............................................................................................ ....................................53 register 8 (0x08): global cont rol 6 ............................................................................................ ....................................53 register 9 (0x09): global cont rol 7 ............................................................................................ ....................................53 register 10 (0x0a): global cont rol 8........................................................................................... ...................................53 register 11 (0x0b): global cont rol 9........................................................................................... ...................................53 register 12 (0x0c): reserved r egist er.......................................................................................... ................................54 register 13 (0x0d): user defined regi ster 1 .................................................................................... .............................54 register 14 (0x0e): user defined regi ster 2 .................................................................................... .............................54 register 15 (0x0f): user defined re gister 3 .................................................................................... .............................54 port regi sters......................................................................................................................................................................55 register 16 (0x10): port 1 co ntrol 0........................................................................................... ....................................55 register 32 (0x20): port 2 co ntrol 0........................................................................................... ....................................55 register 48 (0x30): port 3 co ntrol 0........................................................................................... ....................................55 register 17 (0x11): port 1 co ntrol 1........................................................................................... ....................................56 register 33 (0x21): port 2 co ntrol 1........................................................................................... ....................................56 register 49 (0x31): port 3 co ntrol 1........................................................................................... ....................................56 register 18 (0x12): port 1 co ntrol 2........................................................................................... ....................................57 register 34 (0x22): port 2 co ntrol 2........................................................................................... ....................................57 register 50 (0x32): port 3 co ntrol 2........................................................................................... ....................................57 register 19 (0x13): port 1 co ntrol 3........................................................................................... ....................................57 register 35 (0x23): port 2 co ntrol 3........................................................................................... ....................................57 register 51 (0x33): port 3 co ntrol 3........................................................................................... ....................................57 register 20 (0x14): port 1 co ntrol 4........................................................................................... ....................................58 register 36 (0x24): port 2 co ntrol 4........................................................................................... ....................................58 register 52 (0x34): port 3 co ntrol 4........................................................................................... ....................................58 register 21 (0x15): port 1 co ntrol 5........................................................................................... ....................................58 register 37 (0x25): port 2 co ntrol 5........................................................................................... ....................................58 register 53 (0x35): port 3 co ntrol 5........................................................................................... ....................................58 register 22 (0x16): port 1 co ntrol 6........................................................................................... ....................................58 register 38 (0x26): port 2 co ntrol 6........................................................................................... ....................................58 register 54 (0x36): port 3 co ntrol 6........................................................................................... ....................................58 register 23 (0x17): port 1 co ntrol 7........................................................................................... ....................................58 register 39 (0x27): port 2 co ntrol 7........................................................................................... ....................................58 register 55 (0x37): port 3 co ntrol 7........................................................................................... ....................................58 register 24 (0x18): port 1 co ntrol 8........................................................................................... ....................................58 register 40 (0x28): port 2 co ntrol 8........................................................................................... ....................................58 register 56 (0x38): port 3 co ntrol 8........................................................................................... ....................................58 register 25 (0x19): port 1 co ntrol 9........................................................................................... ....................................59 register 41 (0x29): port 2 co ntrol 9........................................................................................... ....................................59 register 57 (0x39): port 3 co ntrol 9........................................................................................... ....................................59 register 26 (0x1a): port 1 c ontrol 10 .......................................................................................... ..................................59 register 42 (0x2a): port 2 c ontrol 10 .......................................................................................... ..................................59 register 58 (0x3a): port 3 c ontrol 10 .......................................................................................... ..................................59 register 27 (0x1b): port 1 c ontrol 11 .......................................................................................... ..................................59 downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 8 m9999-020606 register 43 (0x2b): port 2 c ontrol 11 .......................................................................................... ..................................59 register 59 (0x3b): port 3 c ontrol 11 .......................................................................................... ..................................59 register 28 (0x1c): port 1 co ntrol 12 .......................................................................................... ..................................60 register 44 (0x2c): port 2 co ntrol 12 .......................................................................................... ..................................60 register 60 (0x3c): reserv ed, not applied to port 3 ............................................................................ ..........................60 register 29 (0x1d): port 1 co ntrol 13 .......................................................................................... ..................................61 register 45 (0x2d): port 2 co ntrol 13 .......................................................................................... ..................................61 register 61 (0x3d): reserv ed, not applied to port 3 ............................................................................ ..........................61 register 30 (0x1e): port 1 st atus 0............................................................................................ ....................................62 register 46 (0x2e): port 2 st atus 0............................................................................................ ....................................62 register 62 (0x3e): reserv ed, not applied to port 3 ............................................................................ ..........................62 register 31 (0x1f): port 1 st atus 1 ............................................................................................ ....................................63 register 47 (0x2f): port 2 st atus 1 ............................................................................................ ....................................63 register 63 (0x3f): port 3 st atus 1 ............................................................................................ ....................................63 advanced contro l regist ers ..............................................................................................................................................64 register 96 (0x60): tos prio rity control register 0............................................................................ ...........................64 register 97 (0x61): tos prio rity control register 1............................................................................ ...........................64 register 98 (0x62): tos prio rity control register 2............................................................................ ...........................64 register 99 (0x63): tos prio rity control register 3............................................................................ ...........................64 register 100 (0x64): tos prio rity control register 4........................................................................... ..........................64 register 101 (0x65): tos prio rity control register 5........................................................................... ..........................64 register 102 (0x66): tos prio rity control register 6........................................................................... ..........................64 register 103 (0x67): tos prio rity control register 7........................................................................... ..........................64 register 104 (0x68): mac address regi ster 0 .................................................................................... ..........................65 register 105 (0x69): mac address regi ster 1 .................................................................................... ..........................65 register 106 (0x6a): mac address regi ster 2 .................................................................................... ..........................65 register 107 (0x6b): mac address regi ster 3 .................................................................................... ..........................65 register 108 (0x6c): mac address regi ster 4.................................................................................... ..........................65 register 109 (0x6d): mac address regi ster 5 .................................................................................... .........................65 register 110 (0x6e): indi rect access control 0................................................................................. .............................66 register 111 (0x6f): indi rect access control 1................................................................................. .............................66 register 112 (0x70): indire ct data re gister 8 .................................................................................. ..............................66 register 113 (0x71): indire ct data re gister 7 .................................................................................. ..............................66 register 114 (0x72): indire ct data re gister 6 .................................................................................. ..............................66 register 115 (0x73): indire ct data re gister 5 .................................................................................. ..............................66 register 116 (0x74): indire ct data re gister 4 .................................................................................. ..............................66 register 117 (0x75): indire ct data re gister 3 .................................................................................. ..............................67 register 118 (0x76): indire ct data re gister 2 .................................................................................. ..............................67 register 119 (0x77): indire ct data re gister 1 .................................................................................. ..............................67 register 120 (0x78): indire ct data re gister 0 .................................................................................. ..............................67 registers 121 to 127 ......................................................................................................................................................67 static mac a ddress t able .............................................................................................................................................67 vlan t able....................................................................................................................................................................68 dynamic mac a ddress t able ...................................................................................................... ..................................69 mib (management informa tion base) counters ..................................................................................... ........................70 additional in formation.....................................................................................................................................................73 absolute maximum ratings....................................................................................................... ..........74 operating ratings.............................................................................................................. ...................74 electrical characteristics .....................................................................................................................75 timing specifications...........................................................................................................................77 eeprom ti ming ..................................................................................................................................................................77 sni timing..................................................................................................................... .......................................................78 mii timing.78 mac mode m ii timing............................................................................................................ ........................................79 phy-mode m ii timing ............................................................................................................ ........................................80 spi timing....78 input ti ming ...................................................................................................................................................................81 output timing.................................................................................................................................................................82 reset ti ming................................................................................................................... .....................................................83 selection of isolation transformers............................................................................................ ........85 selection of reference crystal ............................................................................................................85 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micrel, inc. ksz8993m/ml october 2008 9 m9999-020606 package information.............................................................................................................................86 list of figures figure 1. typical strai ght cable co nnection .......................................................................................................................................25 figure 2. typical crosso ver cable connection ................................................................................... ................................................25 figure 3. auto negotiati on and parallel operation .............................................................................. ...............................................26 figure 4. destination address lookup flow char t, stag e 1 ....................................................................... .......................................27 figure 5. destination address resolution flow chart, stage 2 ................................................................... .....................................28 figure 6. 802.1p prio rity fiel d format ......................................................................................... .........................................................37 figure 7. ksz8993m eeprom c onfiguration ti ming diag ram......................................................................... .................................38 figure 8. spi writ e data cycle................................................................................................. ..............................................................42 figure 9. spi read data cycle .................................................................................................. .............................................................42 figure 10. spi mu ltiple write.................................................................................................. ................................................................42 figure 11. spi mu ltiple read................................................................................................... ...............................................................43 figure 12. loo pback path ....................................................................................................... ...............................................................44 figure 13. eeprom interf ace input timi ng diag ram ............................................................................... ...........................................76 figure 14. eeprom interface output timi ng diag ram .............................................................................. .........................................76 figure 15. sni input timing di agram....................................................................................................................................................77 figure 16. sni output timing di agram.................................................................................................................................................77 figure 17. mac-mode mii timing C data receive d from mii ........................................................................ ......................................79 figure 18. mac-mode mii timi ng C data input to mii ............................................................................. .............................................78 figure 19. phy-mode mii timing C data received from mii ........................................................................ .......................................79 figure 20. phy-mode mii timi ng C data input to mii............................................................................. ..............................................79 figure 21. spi input ti ming.................................................................................................... ................................................................81 figure 22. spi ou tput ti ming.................................................................................................................................................................82 figure 23. r eset timing ........................................................................................................ .................................................................83 128-pin pqfp packa ge...........................................................................................................................................................................86 list of tables table 1. fx and tx mode selection .............................................................................................. ........................................................22 table 2. mdi/mdi-x pin definitions............................................................................................. ...........................................................23 table 3. m ii signals ........................................................................................................... ......................................................................31 table 4. sn i signals ........................................................................................................... .....................................................................32 table 5. mii management interface fr ame format ................................................................................. .............................................33 table 6. serial management interface (smi) frame for mat........................................................................ ........................................33 table 7. upstream special tagging mo de format .................................................................................. ............................................35 table 8. stpid egress rules (s witch port 3 to processor)....................................................................... .........................................35 table 9. fid+da look up in vlan mode ............................................................................................ ...................................................37 table 10. fid+sa look up in vlan mode ........................................................................................... ..................................................37 table 11. ksz8993m spi conn ections............................................................................................. .....................................................41 table 12. format of static mac table (8 entries)............................................................................... .................................................67 table 13. format of static vlan table ( 16 entr ies) ............................................................................................................................69 table 14. format of dynamic ma c address table (1k entr ies) ..................................................................... ...................................69 table 15. format of per port mib counters.................................................................................... ..................................................70 table 16. port 1s per port mib co unters indirect me mory offsets.............................................................. ..................................71 table 17. port 1s per port mib counters indirect memory offsets............................................................. ..................................72 table 18. format of all port dropped packet mib counters ..................................................................... .....................................72 table 19. all port dropped packet mi b counters indirect memory offsets ....................................................... ..........................72 table 20. eeprom timing para meters ................................................................................................................................................77 table 21. sni ti ming para meters ..........................................................................................................................................................78 table 22. mac-mode m ii timing pa rameters ....................................................................................... ................................................79 table 23. phy-mode m ii timing pa rameters ....................................................................................... .................................................80 table 24. spi input timing para meters ................................................................................................................................................81 table 25. spi output timing pa rameters ......................................................................................... ....................................................82 table 26. reset ti ming para meters ......................................................................................................................................................83 table 27. transformer selection criteria..............................................................................................................................................85 table 28. qualified si ngle port magneti cs ...........................................................................................................................................85 table 29. typical referenc e crystal char acteristics ............................................................................ ..............................................85 downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 10 m9999-020606 pin description and i/o assignment pin number pin name type (1) description 1 2 3 p1led2 p1led1 p1led0 ipu/o ipu/o ipu/o port 1 led indicators [ledsel1, ledsel0] [0, 0] [0, 1] p1led3 p1led2 link/act 100link/act p1led1 full duplex/col 10link/act p1led0 speed full duplex [ledsel1, ledsel0] [1, 0] [1, 1] p1led3 act p1led2 link p1led1 full duplex/col p1led0 speed notes: ledsel0 is external strap-in pin 70. ledsel1 is external strap-in pin 23. p1led3 is pin 25. during reset, p1led[2:0] ar e inputs for internal testing. 4 5 6 p2led2 p2led1 p2led0 ipu/o ipu/o ipu/o port 2 led indicators [ledsel1, ledsel0] [0, 0] [0, 1] p2led3 p2led2 link/act 100link/act p2led1 full duplex/col 10link/act p2led0 speed full duplex [ledsel1, ledsel0] [1, 0] [1, 1] p2led3 act p2led2 link p2led1 full duplex/col p2led0 speed notes: ledsel0 is external strap-in pin 70. ledsel1 is external strap-in pin 23. p2led3 is pin 20. during reset, p2led[2:0] ar e inputs for internal testing. 7 dgnd gnd digital ground note: 1. ipu/o = input with internal pull-up during reset, output pin otherwise. gnd = ground. downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 11 m9999-020606 pin number pin name type (1) description 8 vddio p 3.3v digital v dd 9 nc ipd no connect 10 nc ipd no connect 11 nc ipu no connect 12 advfc ipu 1 = advertise the switchs flow control capability via auto negotiation. 0 = will not advertise the switchs flow control capability via auto negotiation. 13 p2anen ipu 1 = enable auto negotiation on port 2 0 = disable auto negotiation on port 2 14 p2spd ipd 1 = force port 2 to 100bt if p2anen = 0 0 = force port 2 to 10bt if p2anen = 0 15 p2dpx ipd 1 = port 2 default to full duplex mode if p2anen = 1 and auto negotiation fails. force port 2 in full duplex mode if p2anen = 0. 0 = port 2 default to half duplex mode if p2anen = 1 and auto negotiation fails. force port 2 in half duplex mode if p2anen = 0. 16 p2ffc ipd 1 = always enable (for ce) port 2 flow control feature 0 = port 2 flow control featur e enable is determined by auto negotiation result. 17 nc opu no connect 18 nc ipd no connect 19 nc ipd no connect 20 p2led3 opd port 2 led indicator note: internal pull-down is weak ; it will not turn on the led. see description in pin 4. 21 dgnd gnd digital ground 22 vddc/vout_1 v8 p v ddc : for ksz8993m, this is an input power pin for the 1.8v digital core v dd . v out_1v8 : for ksz8993ml, this is a 1.8v output power pin to supply the ksz8993mls input power pins: v ddap (pin 63), v ddc (pins 91 and 123), and v dda (pins 38, 43, and 57). 23 ledsel1 ipd led display mode select see description in pins 1 and 4. 24 nc o no connect 25 p1led3 opd port 1 led indicator note: an external 1k pull-down is needed on this pin if it is connected to a led. the 1k resistor will not turn on the led. see description in pin 1. note: 1. p = power supply. gnd = ground. o = output. ipu = input w/ internal pull-up. ipd = input w/ internal pull-down. opu = output with internal pull-up. opd = output internal pull-down. downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 12 m9999-020606 pin number pin name type (1) description 26 nc o no connect 27 hwpovr ipd hardware pin overwrite 0 = disable. all strap-in pins c onfigurations are overwritten by the eeprom config uration data 1 = enable. all strap-in pins co nfigurations are overwritten by the eeprom configuratio n data, except for register 0x2c bits [7:5], (port 2: auto-negotiation enable, force speed, force duplex). 28 p2mdixdis ipd port 2 auto mdi/mdi-x pd (default) = enable pu = disable 29 p2mdix ipd port 2 mdi/mdi-x setti ng when auto mdi/mdi-x is disabled. pd (default) = mdi-x (transmit on txp2 / txm2 pins) pu = mdi, (transmit on rxp2 / rxm2 pins) 30 p1anen ipu 1 = enable auto negotiation on port 1 0 = disable auto negotiation on port 1 31 p1spd ipd 1 = force port 1 to 100bt if p1anen = 0 0 = force port 1 to 10bt if p1anen = 0 32 p1dpx ipd 1 = port 1 default to full duplex mode if p1anen = 1 and auto negotiation fails. force port 1 in full-duplex mode if p1anen = 0. 0 = port 1 default to half duplex mode if p1anen = 1 and auto negotiation fails. force port 1 in half duplex mode if p1anen = 0. 33 p1ffc ipd 1 = always enable (for ce) port 1 flow control feature 0 = port 1 flow control featur e enable is determined by auto negotiation result. 34 nc ipd no connect 35 nc ipd no connect 36 pwrdn ipu chip power-down input (active low) 37 agnd gnd analog ground 38 vdda p 1.8v analog v dd 39 agnd gnd analog ground 40 mux1 i factory test pin - float for normal operation 41 mux2 i factory test pin - float for normal operation 42 agnd gnd analog ground 43 vdda p 1.8v analog v dd 44 fxsd1 i fiber signal detect/factory test pin note: 1. p = power supply. gnd = ground. i = input. o = output. ipu = input w/ internal pull-up. ipd = input w/ internal pull-down. downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 13 m9999-020606 pin number pin name type (1) description 45 rxp1 i/o physical receive or transmit signal (+ differential) 46 rxm1 i/o physical receive or transmit signal (C differential) 47 agnd gnd analog ground 48 txp1 i/o physical transmit or receive signal (+ differential) 49 txm1 i/o physical transmit or receive signal (C differential) 50 vddatx p 3.3v analog v dd 51 vddarx p 3.3v analog v dd 52 rxm2 i/o physical receive or transmit signal (C differential) 53 rxp2 i/o physical receive or transmit signal (+ differential) 54 agnd gnd analog ground. 55 txm2 i/o physical transmit or receive signal (C differential) 56 txp2 i/o physical transmit or receive signal (+ differential) 57 vdda p 1.8 analog v dd 58 agnd gnd analog ground 59 test1 i factory test pin - float for normal operation 60 test2 ipu factory test pin - float or pull-up for normal operation 61 iset o set physical transmit output current. pull-down this pin with a 3.01k 1% resistor to ground. 62 agnd gnd analog ground 63 vddap p 1.8v analog v dd for pll 64 agnd gnd analog ground. 65 66 x1 x2 i o 25mhz crystal/oscillator clock connections pins (x1, x2) connect to a crystal. if an oscillator is used, x1 connects to a 3.3v tolerant oscillator and x2 is a no connect. note: clock is +/- 50ppm for both crystal and oscillator. 67 rst_n ipu hardware reset pin (active low) 68 bpen ipd half-duplex backpressure 1 = enable 0 = disable 69 smac ipd special mac-mode in this mode, the switch will do faster back-offs than normal. 1 = enable 0 = disable note: 1. p = power supply. gnd = ground. i = input. o = output. ipu = input w/ internal pull-up. ipd = input w/ internal pull-down. downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 14 m9999-020606 pin number pin name type (1) description 70 ledsel0 ipd led display mode select see description in pins 1 and 4. 71 smtxen ipd switch mii transmit enable 72 smtxd3 ipd switch mii transmit data bit 3 73 smtxd2 ipd switch mii transmit data bit 2 74 smtxd1 ipd switch mii transmit data bit 1 75 smtxd0 ipd switch mii transmit data bit 0 76 smtxer ipd switch mii transmit error 77 smtxc ipd/o switch mii transmit clock output in phy mii mode input in mac mii mode 78 dgnd gnd digital ground 79 vddio p 3.3v digital v dd 80 smrxc ipd/o switch mii receive clock. output in phy mii mode input in mac mii mode 81 smrxdv o switch mii receive data valid 82 smrxd3 ipd/o switch mii receive data bit 3 strap option: switch mii full-duplex flow control pd (default) = disable pu = enable 83 smrxd2 ipd/o switch mii receive bit 2 strap option: switch mii is in pd (default) = full-duplex mode pu = half-duplex mode 84 smrxd1 ipd/o switch mii receive bit 1 strap option: switch mii is in pd (default) = 100mbps mode pu = 10mbps mode 85 smrxd0 ipd/o switch mii receive bit 0 strap option: switch will accept packet size up to pd (default) = 1536 bytes (inclusive) pu = 1522 bytes (tagged), 1518 bytes (untagged) 86 scol ipd/o switch mii collision detect 87 scrs ipd/o switch mii carrier sense note: 1. p = power supply. gnd = ground. o = output. ipd = input w/ internal pull-down. ipd/o = input w/ internal pull-down during reset, output pin otherwise. downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 15 m9999-020606 pin number pin name type (1) description 88 89 sconf1 sconf0 ipd ipd switch mii interface configuration (sconf1, sconf0) description (0,0) disable, outputs tri-stated (0,1) phy mode mii (1,0) mac mode mii (1,1) phy mode sni 90 dgnd gnd digital ground 91 vddc p 1.8v digital vdd 92 93 prsel1 prsel0 ipd ipd priority select. select queue servicing if using split queues. use the table below to select t he desired servicing. note that this selection effects all split transmit queue ports in the same way. (prsel1, prsel0) description (0,0) transmit all high priority before low priority (0,1) transmit high priority and low priority at 10:1 ratio. (1,0) transmit high priority and low priority at 5:1 ratio. (1,1) transmit high priority and low priority at 2:1 ratio. 94 mdc ipu mii management interface: clock input 95 mdio ipu/o mii management interface: data input/output note: an external 4.7k pull-up is needed on this pin when it is in use. 96 spiq opu spi slave mode: serial data output see description in pins 100 and 101. 97 scl ipu/o spi slave mode / i 2 c slave mode: clock input i 2 c master mode: clock output see description in pins 100 and 101. 98 sda ipu/o spi slave mode: serial data input i 2 c master/slave mode: serial data input/output see description in pins 100 and 101. 99 spis_n ipu spi slave mode: chip select (active low) when spis_n is high, the ksz8993m is deselected and spiq is held in high impedance state. a high-to-low transition is used to initiate spi data transfer. see description in pins 100 and 101. note: 1. p = power supply. gnd = ground. ipu = input w/ internal pull-up. ipd = input w/ internal pull-down. ipu/o = input w/ internal pull-up during reset, output pin otherwise. opu = output w/ internal pull-up. downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 16 m9999-020606 pin number pin name type (1) description 100 101 ps1 ps0 ipd ipd serial bus configuration pins to select mode of access to ksz8993m internal registers. [ps1, ps0] = [0, 0] i 2 c master (eeprom) mode (if eeprom is not detected, t he power-up default values of the ksz8993m internal registers will be used.) interface signals type description spiq o not used (tri-stated) scl o i 2 c clock sda i/o i 2 c data i/o spis_n ipu not used [ps1, ps0] = [0, 1] i 2 c slave mode the external i 2 c master will drive the scl clock. the ksz8993m device addresses are: 1011_1111 1011_1110 interface signals type description spiq o not used (tri-stated) scl i i 2 c clock sda i/o i 2 c data i/o spis_n ipu not used [ps1, ps0] = [1, 0] spi slave mode interface signals type description spiq o spi data out scl i spi clock sda i spi data in spis_n ipu spi chip select [ps1, ps0] = [1, 1] C smi-mode in this mode, the ksz8993m provides access to all its internal 8 bit registers through its mdc and mdio pins. note: when (ps1, ps0) (1,1), the ksz8993m provides access to its 16 bit miim registers through its mdc and mdio pins. 102 103 pv31 pv32 ipu ipu port 3 port-based vlan mask bits C use to select which ports may transmit packets received on port 3. pv31 = 1, port 1 may transmit packets received on port 3 pv31 = 0, port 1 will not transmit any packets received on port 3 pv32 = 1, port 2 may transmit packets received on port 3 pv32 = 0, port 2 will not transmit any packets received on port 3 note: 1. i = input. ipu = input w/ internal pull-up. i/o = bi-directional. o= output. ipd = input w/ internal pull-down. downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 17 m9999-020606 pin number pin name type (1) description 104 105 pv21 pv23 ipu ipu port 2 port-based vlan mask bits C use to select which ports may transmit packets received on port 2. pv21 = 1, port 1 may transmit packets received on port 2 pv21 = 0, port 1 will not transmit any packets received on port 2 pv23 = 1, port 3 may transmit packets received on port 2 pv23 = 0, port 3 will not transmit any packets received on port 2 106 dgnd gnd digital ground 107 vddio p 3.3v digital v dd 108 109 pv12 pv13 ipu ipu port 1 port-based vlan mask bits C use to select which ports may transmit packets received on port 1. pv12 = 1, port 2 may transmit packets received on port 1 pv12 = 0, port 2 will not transmit any packets received on port 1 pv13 = 1, port 3 may transmit packets received on port 1 pv13 = 0, port 3 will not transmit any packets received on port 1 110 p3_1pen ipd enable 802.1p priority cl assification on port 3 ingress 1 = enable 0 = disable enable is from the receive perspective. if 802.1p processing is disabled or there is no tag, priority is determined by the p3_pp pin. 111 p2_1pen ipd enable 802.1p priority cl assification on port 2 ingress 1 = enable 0 = disable enable is from the receive perspective. if 802.1p processing is disabled or there is no tag, priority is determined by the p2_pp pin. 112 p1_1pen ipd enable 802.1p priority cl assification on port 1 ingress 1 = enable 0 = disable enable is from the receive perspective. if 802.1p processing is disabled or there is no tag, priority is determined by the p1_pp pin. 113 p3_txq2 ipd select transmit queue split on port 3 1 = split 0 = no split the split sets up high and low priority queues. packet priority classification is done on ingress ports, via port-based, 802.1p or tos based scheme. the priority enabled queuing on port 3 is set by p3_txq2. note: 1. p = power supply. gnd = ground. ipu = input w/ internal pull-up. ipd = input w/ internal pull-down. downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 18 m9999-020606 pin number pin name type (1) description 114 p2_txq2 ipd select transmit queue split on port 2 1 = split 0 = no split the split sets up high and low priority queues. packet priority classification is done on ingress ports, via port-based, 802.1p or tos based scheme. the priority enabled queuing on port 2 is set by p2_txq2. 115 p1_txq2 ipd select transmit queue split on port 1 1 = split 0 = no split the split sets up high and low priority queues. packet priority classification is done on ingress ports, via port-based, 802.1p or tos based scheme. the priority enabled queuing on port 1 is set by p1_txq2. 116 p3_pp ipd select port-based priority on port 3 ingress 1 = high 0 = low 802.1p and diffserv, if applicable, takes precedence. 117 p2_pp ipd select port-based priority on port 2 ingress 1 = high 0 = low 802.1p and diffserv, if applicable, takes precedence. 118 p1_pp ipd select port-based priority on port 1 ingress 1 = high 0 = low 802.1p and diffserv, if applicable, takes precedence. 119 p3_tagins ipd enable tag insertion on port 3 egress 1 = enable 0 = disable all packets transmitted from port 3 will have 802.1q tag. packets received with tag will be sent out intact. packets received without tag will be tagged with ingress ports default tag. 120 p2_tagins ipd enable tag insertion on port 2 egress 1 = enable 0 = disable all packets transmitted from port 2 will have 802.1q tag. packets received with tag will be sent out intact. packets received without tag will be tagged with ingress ports default tag. note: 1. ipd = input w/ internal pull-down. downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 19 m9999-020606 pin number pin name type (1) description 121 p1_tagins ipd enable tag insertion on port 1 egress 1 = enable 0 = disable all packets transmitted from port 1 will have 802.1q tag. packets received with tag will be sent out intact. packets received without tag will be tagged with ingress ports default tag. 122 dgnd gnd digital ground 123 vddc p 1.8v digital v dd 124 p3_tagrm ipd enable tag removal on port 3 egress 1 = enable 0 = disable all packets transmitted from port 3 will not have 802.1q tag. packets received with tag will be modified by removing 802.1q tag. packets received without tag will be sent out intact. 125 p2_tagrm ipd enable tag removal on port 2 egress 1 = enable 0 = disable all packets transmitted from port 2 will not have 802.1q tag. packets received with tag will be modified by removing 802.1q tag. packets received without tag will be sent out intact. 126 p1_tagrm ipd enable tag removal on port 1 egress 1 = enable 0 = disable all packets transmitted from port 1 will not have 802.1q tag. packets received with tag will be modified by removing 802.1q tag. packets received without tag will be sent out intact. 127 testen ipd scan test enable for normal operation, pull-down this pin to ground. 128 scanen ipd scan test scan mux enable for normal operation, pull-down this pin to ground. note: 1. p = power supply. gnd = ground. ipd = input w/ internal pull-down. downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 20 m9999-020606 pin configuration pv31ps0 ps1 spis_n sda scl spiq mdio mdc prsel0 prsel1 vddc dgnd sconf0 sconf1 scrs scol smrxd0 smrxd1 smrxd2 smrxd3 smrxdv smrxc vddio dgnd smtxc smtxer smtxd0 smtxd1 smtxd2 smtxd3 smtxen ledsel0 smac bpen rst_n x2 x1 p1led2 p1led1 p1led0 p2led2 p2led1 p2led0 dgnd vddio ncnc nc advfc p2anen p2spdp2dpx p3ffc ncnc nc p2led3 dgnd vddc ledsel1 nc p1led3 nc hwpovr p2mdixdi s p2mdix p1anen p1spdp1dpx p1ffc ncnc pwrdn agnd vdda agndvddap agnd iset test2 test1 agnd vdda txp2 txm2 agnd rxp2 rxm2 vddarx vddatx txm1 txp1 agnd rxm1 rxp1 fxsd1 vdda agnd mux2 mux1 agnd pv32pv21 pv23 dgnd vddio pv12pv13 p3_1pen p2_1pen p1_1pen p3_txq2 p2_txq2 p1_txq2 p3_ppp2_pp p1_pp p3_tagins p2_tagins p1_tagins dgnd vddc p3_tagrm p2_tagrm p1_tagrm testen scanen 128-pin pqfp (top view) downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 21 m9999-020606 functional description the ksz8993m contains two 10/100 physical layer transceiv ers and three mac units with an integrated layer 2 managed switch. the ksz8993m has the flexibility to reside in either a managed or unmanaged design. in a managed design, the host processor has complete control of the ksz8993m via the smi interface, miim interface, spi bus, or i 2 c bus. an unmanaged design is achieved through i/o strapping and/or eeprom programming at system reset time. on the media side, the ksz8993m supports ieee 802.3 10base-t and 100base-tx on both phy ports, and 100base-fx on phy port 1. the ksz8993m c an be used as a me dia converter. the ksz8993ml is the single supply version with all the identical rich features of the ksz8993m. in the ksz8993ml version, pin number 22 provides 1.8v output power to the ksz8993mls v ddc , v dda , and v ddap power pins. refer to the pin description table for inform ation about pin 22 (pin description and i/0 assignment). physical signal transmission and reception are enhanced through the use of patented analog circuitries that make the design more efficient and allow for lower po wer consumption and smaller chip die size. functional overview: phys ical layer transceiver 100base-tx transmit the 100base-tx transmit function performs parallel to se rial conversion, 4b/5b coding, scrambling, nrz to nrzi conversion, mlt3 encoding and trans mission. the circuit starts with a parallel-to-serial conversion, which converts the mii data from the mac into a 125mhz seri al bit stream. the data and control stream is then converted into 4b/5b coding and followed by a scrambler. the serialized data is further converted from nrz to nrzi format, and then transmitted in mlt3 current output. the output current is set by an external 1% 3.01 k ? resistor for the 1:1 transformer ratio. it has a typical rise/fall time of 4ns and complies with the ansi tp-pmd standard regarding amplitude balance, overshoot, and timi ng jitter. the wave-shape d 10base-t output is also incorporated into the 100base-tx transmitter. 100base-tx receive the 100base-tx receiver function pe rforms adaptive equalizati on, dc restoration, mlt3 to nrzi conversion, data and clock recovery, nrzi to nrz conversion, de-scrambling, 4b/5b decoding and serial-to-parallel conversion. the receiving side starts wi th the equalization filter to compensate for inter-symbol interference (isi) over the twisted pair cable. since the amplitude loss and phase distortion is a function of the length of the cable, the equalizer has to adjust its characteri stics to optimize the performance. in this design, the variable equalizer will make an initial estimation based on comparisons of incoming signal strength against some known cable characteristics, then it tunes itse lf for optimization. this is an ongoi ng process and can self adjust against environmental changes such as temperature variations. the equalized signal then goes through a dc restoration and dat a conversion block. the dc restoration circuit is used to compensate for the effect of base line wander and improve the dynamic range. the differential data conversion circuit converts the mlt3 format back to nrzi. the slicing threshold is also adaptive. the clock recovery circuit extracts t he 125mhz clock from the edges of the nrzi signal. this recovered clock is then used to convert the nrzi signal into the nrz form at. the signal is then sent through the de-scrambler followed by the 4b/5b decoder. finally, the nrz serial dat a is converted to the mii format and provided as the input data to the mac. downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 22 m9999-020606 pll clock synthesizer the ksz8993m generates 125mhz, 31.25mhz, 25mhz, and 10mh z clocks for system timing. internal clocks are generated from an external 25mhz crystal or oscillator. scrambler/de-scrambler (100base-tx only) the purpose of the scrambler is to spread the power spectrum of the signal in order to reduce emi and baseline wander. transmitted data is scrambled through the use of an 11-bit wide linear feedback shift register (lfsr). the scrambler can generate a 2047-bit non-repetitive sequence. the receiver will then de-scramble the incoming data stream with the same sequence at the transmitter. 100base-fx operation 100base-fx operation is very similar to 100base-tx operation with the differe nces being that the scrambler / de-scrambler and mlt3 encoder / dec oder are bypassed on transmission an d reception. in 100base-fx mode, the auto negotiation feature is bypassed since there is no standard that supports fiber auto negotiation. the auto- mdi/mdi-x feature is also disabled. 100base-fx signal detection in fiber operation, the ksz8993ms fxsd1 (fiber signal detect) input pin is usually connected to the fiber transceivers sd (signal de tect) output pin. 100base-fx mode is activat ed when the fxsd1 input pin is greater than 1v. when fxsd1 is between 1v and 1.8v, no fiber signal is detected and a far end fault (fef) is generated. when fxsd1 is over 2.2v, the fiber signal is detected. alternatively, the designer may choose not to implement the fef feature. in this case, the fxsd1 input pin is tied high to force 100base-fx mode. 100base-fx signal detection is summarized in the following table: part number mode less than 0.2v tx mode greater than 1v, but less than 1.8v fx mode no signal detected. far-end fault generated greater than 2.2v i fx mode signal detected table 1. fx and tx mode selection to ensure proper operation, a resistive voltage divider is recommended to adjust the fiber transceivers sd output voltage swing to match the ksz8993ms fxsd1 input voltage threshold. 100base-fx far end fault an fef occurs when the signal detection is logically fa lse on the receive side of the fiber transceiver. the ksz8993m detects a fef when its fxsd1 input is bet ween 1.0v and 1.8v. when an fef occurs, the transmission side signals the other end of the link by sending 84 1s followed by a zero in the idle period between frames. upon receiving an fef, the link will go down (even when a fi ber signal is detected) to indicate a fault condition. the transmitting side is not affected when an fef is rece ived, and will continue to send out its normal transmit pattern from the mac. by default, fef is enabled. the fef feature can be disabled through register setting. downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 23 m9999-020606 10base-t transmit the output 10base-t driver is incorporated into the 100 base-t driver to allow transmission with the same magnetic. they are internally wave-shaped and pre-emphas ized into outputs with a typical 2.3v amplitude. the harmonic contents are at least 27db below the fundamental when driven by an all-ones manchester-encoded signal. 10base-t receive on the receive side, input buffers and level detecting squel ch circuits are employed. a differential input receiver circuit and a pll perform the decoding function. the ma nchester-encoded data stream is separated into clock signal and nrz data. a squelch circuit rejects signals with levels less than 400 mv or with short pulse widths in order to prevent noises at the rxp or rxm input from fa lsely triggering the decoder. when the input exceeds the squelch limit, the pll locks onto the incoming signal and the ksz8993m decodes a data frame. the receiver clock is maintained active during idle periods in between data reception. power management the ksz8993m features a per-port power down mode. to save power, the user can power down ports that are not in use by setting the port control r egisters, or mii control registers. in addition, there is a full chip power down mode. when activated, the entire chip will be shut down. mdi /mdi-x auto crossover the ksz8993m supports mdi/ di-x auto cr ossover. this facilitates the use of either a straight connection cat-5 cable or a crossover cat-5 cable. the auto-sense function will detect remote transmit and receive pairs, and correctly assign the transmit and receive pairs from the ksz8993m device. this feature can be extremely useful when end users are unaware of cable types and can also save on an additional uplink configuration connection. the auto-crossover feature can be disabled through the port control registers. based on the ieee 802.3 standard, the mdi and mdi-x definitions are as follows: mdi mdi-x rj45 pins signals rj-45 pins signals 1 td+ 1 rd+ 2 td- 2 rd- 3 rd+ 3 td+ 6 rd- 6 td- table 2. mdi/mdi-x pin definitions downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 24 m9999-020606 straight cable a straight cable connects an mdi device to an mdi-x device, or an mdi-x device to an mdi device. the following diagram depicts a typical straight cable connection between a nic card (mdi) and a switch, or hub (mdi-x). receive pair transmit pair receive pair 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 transmit pair modular connector (rj-45) nic straight cable 10/100 ethernet media dependent interface 10/100 ethernet media dependent interface modular connector (rj-45) hub (repeater or switch) figure 1. typical straight cable connection downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 25 m9999-020606 crossover cable a crossover cable connects an mdi device to another md i device, or an mdi-x devic e to another mdi-x device. the following diagram shows a typical crossover cable connection between two switches or hubs (two mdi-x devices). receive pair receive pair transmit pair 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 transmit pair 10/100 ethernet media dependent interface 10/100 ethernet media dependent interface modular connector (rj-45) hub (repeater or switch) modular connector (rj-45) hub (repeater or switch) crossover cable figure 2. typical crossover cable connection auto negotiation the ksz8993m conforms to the auto negotiation protocol as described by the 802.3 committee. auto negotiation allows unshielded twisted pair (utp) link partners to select the best common mode of operation. in auto negotiation, the link partners advertise capabilities acro ss the link to each other. if auto negotiation is not supported or the link partner to the ksz8993m is forced to bypass auto negotiation, then the mode is set by observing the signal at the receiver. this is known as par allel mode because while the transmitter is sending auto negotiation advertisements, the receiver is listeni ng for advertisements or a fixed signal protocol. the link setup is shown in the following flow diagram. downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 26 m9999-020606 start auto negotiation force link setting listen for 10base-t link pulses listen for 100base-tx idles attempt auto negotiation link mode set bypass auto negotiation and set link mode link mode set ? parallel operation join flow n o ye s yes no figure 3. auto negotiation and parallel operation downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 27 m9999-020606 functional overview : mac and switch address lookup the internal lookup table stores mac addresses and their associated inform ation. it contains a 1k uni-cast address table plus switching information. the ksz8993m is guaranteed to learn 1k addresses and distinguishes itself from hash-based lookup tables, which depending on the operating environment and probabilities, may not guarantee the absolute number of addresses that can be learned. learning the internal lookup engine will update its table with a new entry if the following conditions are met: 1. the received packet's sa does not exist in the lookup table. 2. the received packet is good; the packet has no receiving errors, and is of legal length. the lookup engine will insert the qualified sa into the tabl e, along with the port number and time stamp. if the table is full, the last entry of the table w ill be deleted to make room for the new entry. migration the internal lookup engine also monitors whether a stati on has moved. if so, it will update the table accordingly. migration happens when the following conditions are met: 1. the received packet's sa is in the table but t he associated source port information is different. 2. the received packet is good; the packet has no receiving errors, and is of legal length. the lookup engine will update the exis ting record in the table with t he new source port information. aging the lookup engine will update the time stamp informati on of a record whenever the corresponding sa appears. the time stamp is used in the aging proc ess. if a record is not updated for a pe riod of time, the lookup engine will remove the record from the table. the lookup engine constantly performs the agi ng process and will continuously remove aging records. the aging period is about 200 se conds. this feature can be enabled or disabled through global register 3 (0x03). forwarding the ksz8993m will forward packets using the algorithm that is depicted in the following flowcharts. figure 4 shows stage one of the forwarding algor ithm where the search engine looks up the vlan id, static table, and dynamic table for the destinat ion address, and comes up with port to forw ard 1 (ptf1). ptf1 is then further modified by spanning tree, igmp snooping, port mirrori ng, and port vla processes to come up with port to forward 2 (ptf2), as shown in figure 5. the packet is sent to ptf2. downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 28 m9999-020606 start vlan id valid? ptf1= null search static table search complete. get ptf1 from static mac table dynamic table search search complete. get ptf1 from vlan table search complete. get ptf1 from dynamic mac table ptf1 - search vlan table - ingress vlan filtering - discard npvid check yes no found not found found not found this search is based on da or da+fid this search is based on da+fid figure 4. destination address lookup flow chart, stage 1 downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 29 m9999-020606 spanning tree process ptf1 igmp process port mirror process port vlan membership check ptf2 - check receiving port's receive enable bit - check destination port's transmit enable bit - check whether packets are special (bpdu or specified) - rx mirror - tx mirror - rx or tx mirror - rx and tx mirror - applied to mac #1 and mac #2 - mac #3 is reserved for microprocessor - igmp will be forwarded to port 3 figure 5. destination address resolution flow chart, stage 2 the ksz8993m will not forwar d the following packets: 1. error packets. these include framing errors, fcs er rors, alignment errors, and illegal size packet errors. 2. 802.3x pause frames. the ksz8993m will intercept t hese packets and perform the appropriate actions. 3. "local" packets. based on destination address (da) lookup. if the destination port from the lookup table matches the port where the packet was from , the packet is defined as "local." downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 30 m9999-020606 switching engine the ksz8993m features a high-performance switching engine to move data to and from the macs packet buffers. it operates in store and forward mode, while the efficient switching mechanism reduces overall latency. the ksz8993m has a 32kb internal frame buffer. this resource is shared between all three ports. the buffer- sharing mode can be programmed through global register 2 (0x02). in one mode, ports are allowed to use any free buffers in the buffer pool. in the second mode, each port is only allowed to use one third of the total buffer pool. there are a total of 250 buffers available. each buffer is sized at 128b. mac operation the ksz8993m strictly abides by ieee 802.3 standards to maximize compatibility. inter packet gap (ipg) if a frame is successfully transmitt ed, the 96 bits time ipg is measured between the two consecutive mtxen. if the current packet is experiencing collision, the 96 bits time ipg is measured from mcrs and the next mtxen. back-off algorithm the ksz8993m implements the ieee standard 802.3 bi nary exponential back-off algorithm, and optional "aggressive mode" back-off. after 16 collisions, the packet will be opti onally dropped depending on the chip configuration in global register 3 (0x03) late collision if a transmit packet experiences collisions after 512 bit times of the transmission, the packet will be dropped. illegal frames the ksz8993m discards frames less than 64 bytes and c an be programmed to accept frames up to 1536 bytes in global register 4 (0x04). for special applications, the ksz8993m can also be programmed to accept frames up to 1916 bytes in the same global register. since the ksz8993m supports vlan tags, the maximum sizing is adjusted when these tags are present. see the eeprom section for programming options. flow control the ksz8993m supports standard 802.3x flow c ontrol frames on both transmit and receive sides. on the receive side, if the ksz8993m receives a pause control frame, the ksz8993m will not transmit the next normal frame until the timer, specified in the pause cont rol frame, expires. if another pause frame is received before the current timer expire s, the timer will be updated with the new value in the second pause frame. during this period (being flow controlled), only flow cont rol packets from the ksz8993m will be transmitted. on the transmit side, the ksz8993m has intelligent and effici ent ways to determine when to invoke flow control. the flow control is based on availabilit y of the system resources, includi ng available buffers, available transmit queues and available receive queues. the ksz8993m will flow control a port, which just received a packet, if the destination po rt resource is being used up. the ksz8993m will issue a flow control frame (xoff) , containing the maximum pause time defined in ieee standard 802.3x. once the resource is freed up, the ksz 8993m will send out the other flow control frame (xon) with zero pause time to turn off the flow control (turn on transmission to the port). a hyst eresis feature is provided to prevent the flow control mechanism from being activated and deactivated too many times. the ksz8993m will flow control all ports if the receive queue becomes full. half-duplex ba ckpressure a half-duplex backpressure option (note: not in ieee 802.3 standards) is also provided. the activation and deactivation conditions are the same as the above in full duplex mode. if backpressure is required, the ksz8993m will send preambles to defer the other stations ' transmission (carrier sense deference). to avoid jabber and excessive deference defined in 802.3 standard, after a certain time it will discontinue the carrier sense but it will raise the carrier sense quickly. this short silent time (no carrier sens e) is to prevent ot her stations from downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 31 m9999-020606 sending out packets and keeps other stations in carrier sense deferred state. if the port has packets to send during a backpressure situati on, the carrier sense type bac k pressure will be interrupt ed and those packets will be transmitted instead. if there are no more packets to se nd, carrier sense type backpressure will be active again until switch resources free up. if a collision occurs, the binary exponential back-off algorithm is skipped and carrier sense is generated immediately, reducing the chance of further colliding and maintaining carrier sense to prevent reception of packets. to ensure no packet loss in 10 base-t or 100 base-tx half duplex modes, the user mu st enable the following: 1. aggressive back off (global register 3 (0x03) , bit 0 or external strap-in pin smac = high) 2. no excessive collision drop (global register 4 (0 x04), bit 3 or external strap-in pin smac = high) these bits are not set as defaults because this is not the ieee standard. broadcast storm protection the ksz8993m has an intelligent option to protect the switch system from receiving too many broadcast packets. broadcast packets will be forwarded to all ports except the source port, and thus use too many switch resources (bandwidth and available space in transmit queues). the ksz8993m has the option to include multicast packets for storm control. the broadcast storm rate parameters are programmed globally, and can be enabled or disabled on a per port basis. the rate is based on a 67ms inte rval for 100bt and a 500ms interval for 10bt. at the beginning of each interval, the counter is cleared to zero, and the rate limit mechanism starts to count the number of bytes during the interval. the rate definition is desc ribed in global register 6 (0x06) and 7 (0x07). the default setting for registers 6 and 7 is 0x63, which is 99 decimal. this is equal to a rate of 1%, calculated as follows: 148,800 frames/sec * 67ms/interval * 1% = 99 frames/interval (approx.) = 0x63 mii interface operation the mii is specified by the ieee 802.3 standards committee and provides a common interface between physical layer and mac layer devices. the mii interface provided by the ksz8993m is connected to the devices third mac. the interface contains two distin ct groups of signals: one for transmission and the other for reception. the following table describes the sig nals used in the mii interface. ksz8993m phy-mode connections ksz8993m mac-mode connections external mac controller signals ksz8993m phy signals pin descriptions external phy signals ksz8993m mac signals mtxen smtxen transmit enable mtxen smrxdv mtxer smtxer transmit error mtxer (not used) mtxd3 smtxd[3] transmit data bit 3 mtxd3 smrxd[3] mtxd2 smtxd[2] transmit data bit 2 mtxd2 smrxd[2] mtxd1 smtxd[1] transmit data bit 1 mtxd1 smrxd[1] mtxd0 smtxd[0] transmit data bit 0 mtxd0 smrxd[0] mtxc smtxc transmit clock mtxc smrxc mcol scol collision detection mcol scol mcrs scrs carrier sense mcrs scrs mrxdv smrxdv receive data valid mrxdv smtxen mrxer (not used) receive error mrxer smtxer mrxd3 smrxd[3] receive data bit 3 mrxd3 smtxd[3] mrxd2 smrxd[2] receive data bit 2 mrxd2 smtxd[2] mrxd1 smrxd[1] receive data bit 1 mrxd1 smtxd[1] mrxd0 smrxd[0] receive data bit 0 mrxd0 smtxd[0] mrxc smrxc receive clock mrxc smtxc table 3. mii signals downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 32 m9999-020606 the mii interface operates in either phy mode or mac m ode. the interface is a nibble wide data interfaces and therefore run at ? the network bit rate (not encoded). additional signals on the transmit side indicate when data is valid or when an error occurs during transmission. likewise , the receive side has indicato rs that convey when the data is valid and without physical layer errors. for half dupl ex operation there is a signal that indicates a collision has occurred during transmission. note that the signal mrxer is not provided on the in terface for phy mode operation and the signal mtxer is not provided on the interface for mac mode operation. normally mrxer would indicate a receive error coming from the physical layer device. mtxer would indicate a transmit error from the mac device. these signals are not appropriate for this configuration. for phy mode oper ation, if the device interf acing with the ksz8993m has an mrxer pin, it should be tied low. for mac mode operat ion, if the device interfacing with the ksz8993m has an mtxer pin, it should be tied low. sni (7-wire) operation the serial network interface (sni) or 7-wire is compatible with some cont rollers used for network layer protocol processing. in sni mode, the ksz8993m acts like a phy and the external controller functions as the mac. the ksz8993m can interface directly with external controllers using the 7-wire interfac e. these signals are divided into two groups, one for transmission and the other for reception. the signals in volved are described in the following table. pin descriptions external mac controller signals ksz8993m phy signals transmit enable txen smtxen serial transmit data txd smtxd[0] transmit clock txc smtxc collision detection col scol carrier sense crs smrxdv serial receive data rxd smrxd[0] receive clock rxc smrxc table 4. sni signals the sni interface is a bit wide data interface and theref ore runs at the network bit rate (not encoded). an additional signal on the transmit side indicates when data is valid. similarly, the receive side has an indicator that conveys when the data is valid. for half duplex operation, the ksz8993ms scol signal is used to indicate that a collision has occurred during transmission. mii management interface (miim) the ksz8993m supports the ieee 802. 3 mii management interface, also known as the management data input/output (mdio) interface. this interface allows uppe r-layer devices to monitor and control the states of the ksz8993m. an external device with mdc/mdio capability c an be used to read the phy status or configure the phy settings. further details on the miim interfac e can be found in section 22.2.4.5 of the ieee 802.3 specification. downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 33 m9999-020606 the miim interface consists of the following: ? a physical connection that incorporates t he data line (mdio) and the clock line (mdc). ? a specific protocol that operates across the aforem entioned physical connection that allows an external controller to communicate with the ksz8993m device. ? access to a set of six 16-bits registers, consisting of standard miim registers [0:5]. the following table depicts the mii management interface frame format. preamble start of frame read/write op code phy address bits [4:0] reg address bits [4:0] ta data bits [15:0] idle read 32 1s 01 10 xx0aa rrrrr z0 dddddddd_dddddddd z write 32 1s 01 01 xx0aa rrrrr 10 dddddddd_dddddddd z table 5. mii management interface frame format for the ksz8993m, miim register access is selected when bi t 2 of the phy address is set to 0. phy address bits [4:3] are not defined for miim register access, and hence can be set to either 0s or 1s in read/write operation. serial management interface (smi) the smi is the ksz8993m non-standard miim interface that provides access to all ksz8993m configuration registers. this interface allows an ex ternal device to completely monitor and control the states of the ksz8993m. the smi interface consists of the following: ? a physical connection that incorporates t he data line (mdio) and the clock line (mdc). ? a specific protocol that operates across the afor ementioned physical connection that allows an external controller to communicate with the ksz8993m device. ? access to all ksz8993m configuration registers. registers access includes the global, port and advanced control registers 0-127 (0x00 C 0x7f), and indirect access to the standard miim registers [0:5]. the following table depicts the smi frame format. preamble start of frame read/write op code phy address bits [4:0] reg address bits [4:0] ta data bits [15:0] idle read 32 1s 01 10 rr1xx rrrrr z0 0000_0000_dddd_dddd z write 32 1s 01 01 rr1xx rrrrr 10 xxxx_xxxx_dddd_dddd z table 6. serial management interface (smi) frame format for the ksz8993m, smi register access is selected when bit 2 of the phy address is set to 1. phy address bits [1:0] are not defined for smi register access, and hence can be set to either 0s or 1s in read/write operation. to access the ksz8993m registers 0-127 (0x00 C 0x7f), the following applies: ? phyad[4:3] and regad[4:0] are concatenated to form the 7-bits address; that is, {phyad[4:3], regad[4:0]} = bits [6:0] of the 7-bits address. downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 34 m9999-020606 ? registers are 8 data bits wide. fo r read operation, data bits [15:8] are read back as 0s. for write operation, data bits [15:8] are not defined, and hence can be set to either 0s or 1s. smi register access is the same as the miim register access, except for the register access requirements presented in this section. advanced switch functions spanning tree support to support spanning tree, port 3 is the designated port for the processor. the other ports (port 1 and port 2) can be configured in one of the five spanning tree states via transmit enable, receive enable and learning disable r egister settings in registers 18 and 34 for ports 1 and 2, respectively. the following description shows the port setting and software actions taken for each of the five spanning tree states. disable state: the port should not forward or receive any packets. learning is disabled. port setting: transmit enable = 0, receive enable = 0, learning disable =1 software action: the processor should not send any packets to the port. the swit ch may still send specific packets to the processor (packets that match some entries in the static mac table with overriding bit set) and the processor should disc ard those packets. note: proces sor is connected to port 3 via mii interface. address learning is disabled on the port in this state. blocking state: only packets to the processor are forwarded. learning is disabled. port setting: transmit enable = 0, receive enable = 0, learning disable =1 software action: the processor should not send any packets to the port(s) in this state. the processor should program the static mac table with the entries that it needs to receive (e.g. bpdu packets). the overriding bit should also be set so that the switch will forward those specific packets to the processor. address learning is disabled on the port in this state. listening state: only packets to and from the processor are forwarded. learning is disabled. port setting: transmit enable = 0, receive enable = 0, learning disable =1 software action: the processor should program the static mac tabl e with the entries that it needs to receive (e.g., bpdu packets). the overriding bit should be set so that the switch will forward those specific packets to the processor. the processor may send packets to the port(s) in this st ate, see special tagging mode for details. address l earning is disabled on the port in this state. learning state: only packets to and from the processor are forwarded. learning is enabled. port setting: transmit enable = 0, receive enable = 0, learning disable = 0 downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 35 m9999-020606 software action: the processor should program the static mac tabl e with the entries that it needs to receive (e.g., bpdu packets). the overriding bit should be set so that the switch will forward those specific packets to the processor. the processor may send packets to the port(s) in this st ate, see special tagging mode for details. address learning is enabled on the port in this state. forwarding state: packets are forwarded and received normally. learning is enabled. port setting: transmit enable = 1, receive enable = 1, learning disable = 0 software action: the processor should program the static mac tabl e with the entries that it needs to receive (e.g., bpdu packets). the overriding bit should be set so that the switch will forward those specific packets to the processor. the processor may send packets to the port(s) in this st ate, see special tagging mode for details. address learning is enabled on the port in this state. upstream special tagging mode upstream special tagging mode is designed for spanning tree protocol igmp snooping and is flexible for use in other applications. the upstream special tagging mode, similar to 802.1q, requires software to change network drivers to modify/strip/interpret the sp ecial tag. this mode is enabled by setti ng both register 11 bit 0 and register 48 bit 2 to 1. 802.1q tag format special tag format tpid (tag protocol ident ifier, 0x8100) + tci. stpid (special tag i dentifier, 0x810 + 4 bit for port mask) + tci table 7. upstream special tagging mode format the stpid is only seen and used by the port 3 interface, which should be connected to a processor. the ksz8993m uses a non-zero port mask to bypass the lo okup result and override any port setting, regardless of port states (disable, blocking, listening, learning). for packets from regular ports (port 1 & port 2) to port 3, the port mask is used to tell the processor which port the packets were received on, defined as follows: 0001 from port 1 0010 from port 2 no port mask values, other than the previous two defi ned ones, should be received in upstream special tagging mode. the egress rules are defined as follows: ingress packets egress action to tag field tagged with 0x8100 + tci - modify tpid to 0x810 + port mask, which indicates source port. - no change to tci if vid is not null - replace null vid with ingress port vid - recalculate crc not tagged. - insert tpid to 0x810 + port mask, which indicates source port C insert tci with ingress port vid - recalculate crc table 8. stpid egress rules (switch port 3 to processor) downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 36 m9999-020606 igmp support for igmp support in layer 2, the ksz8993m provides two components: igmp snooping the ksz8993m will trap igmp packets and forward them onl y to the processor (port 3). the igmp packets are identified as ip packets (either ethernet ip packets, or ieee 802.3 snap ip packets) with ip version = 0x4 and protocol version number = 0x2. multicast address insertion in the static mac table once the multicast address is programmed in the static mac table, t he multicast session will be trimmed to the subscribed ports, instead of broadcasting to all ports. to enable igmp support, set register 5 bit 6 to 1. also , special tagging mode needs to be enabled, so that the processor knows which port the igmp packet was received on. this is achiev ed by setting both register 11 bit 0 and register 48 bit 2 to 1. port mirroring support ksz8993m supports port mirroring comprehensively as: 1. receive only mirror on a port all the packets received on the port will be mirrored on the sniffer port. for example, port 1 is programmed to be receive sniff and port 3 is programm ed to be the sniffer port. a packet received on port 1 is destined to port 2 after the internal lookup. the ksz8993m will forward the packet to both port 2 and port 3. the ksz8993m can optionally forward ev en bad received packets to the sniffer port. 2. transmit only mirror on a port all the packets transmitted on the port will be mirrored on the sniffer port. for example, port 1 is programmed to be transmit sniff and port 3 is programmed to be the sniffer port. a packet received on port 2 is destined to port 1 after the internal lookup. the ksz8993m will forward the packet to both port 1 and port 3. 3. receive and transmit mirror on two ports all the packets received on po rt a and transmitted on port b will be mirrored on the sniffer port. to turn on the and feature, set register 5 bit 0 to 1. for example, port 1 is programmed to be receive sniff, port 2 is programmed to be transmit sniff and port 3 is programmed to be the sniffer port. a packet received on port 1 is destined to port 2 after the internal lookup. the ksz8993m will forward the packet to both port 2 and port 3. multiple ports can be selected to be receive sniff or transmit sniff. and any port can be selected to be the sniffer port. all these per port f eatures can be selected through regist ers 17, 33 and 49 for ports 1, 2 and 3, respectively. ieee 802.1q vlan support the ksz8993m supports 16 active vlans out of t he 4096 possible vlans specified in the ieee 802.1q specification. ksz8993m provides a 16-ent ries vlan table, which converts t he 12-bits vlan id (vid) to the 4- bits filter id (fid) for address lookup. if a non-tagged or null-vid-tagged packet is received, the ingress port default vid is used for lookup. in vlan mode, the lookup process starts with vlan table lookup to determine whether the vid is valid. if the vid is not valid, the pac ket will be dropped and its address will not be learned. if the vid is valid, the fid is retrieved for further look up. the fid + destination address (fid+da) are used to determine the destination port. the fid + source ad dress (fid+sa) are used for address learning. downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 37 m9999-020606 da found in static mac table? use fid flag? fid match? da+fid found in dynamic mac table? action no dont care dont care no broadcast to the membership ports defined in the vlan table bits [18:16] no dont care dont care yes send to the destination port defined in the dynamic mac address table bits [53:52] yes 0 dont care dont care send to the destination port(s) defined in the static mac address table bits [50:48] yes 1 no no broadcast to the membership ports defined in the vlan tabl e bits [18:16] yes 1 no yes send to the destination port defined in the dynamic mac address table bits [53:52] yes 1 yes dont care send to the destination port(s) defined in the static mac address table bits [50:48] table 9. fid+da lookup in vlan mode fid+sa found in dynamic mac table? action no learn and add fid+sa to the dynamic mac address table yes update time stamp table 10. fid+sa lookup in vlan mode advanced vlan features, such as ingress vlan filter ing and discard non pvid packets are also supported by the ksz8993m. these features can be set on a per port ba sis, and are defined in register 18, bit 6 and bit 5, respectively for port 1. qos priority support this feature provides quality of service (qos) for applications, such as voip and video conferencing. the ksz8993m per port transmit queue could be split into two priority queues: a high priority queue and a low priority queue. bit 0 of registers 16, 32 and 48 is used to enable sp lit transmit queues for ports 1, 2 and 3, respectively. optionally, the px_txq2 strap-in pins can be used to enable th is feature. with split transmit queues, high priority packets will be placed in the high priority queue and low prio rity packets will be placed in the low priority queue. for split transmit queues, the ksz8993m provides four priority schemes: 1. transmit all high priority packets before low priority packets; i.e. a low priority packet could be transmitted only when the high priority queue is empty 2. transmit high priority packets and low priority packets at 10:1 ratio; i. e. transmit a low priority packet after every 10 high priority packets are transmitted, if both queues are busy 3. transmit high priority packets a nd low priority packets at 5:1 ratio 4. transmit high priority packets a nd low priority packets at 2:1 ratio if a port's transmit queue is not split, both high priority pa ckets and low priority packets have equal priority in the transmit queue. register 5 bits [3:2] are used to select the desired priority scheme. optionally, the prsel1 and prsel0 strap-in pins can be used. downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 38 m9999-020606 port-based priority with port based priority, each ingress port can be individua lly classified as a high priority receiving port. all packets received at the high priority re ceiving port are marked as high priority , and will be sent to the high priority transmit queue if the corresponding transmit queue is spli t. bit 4 of registers 16, 32 and 48 is used to enable port based priority for ports 1, 2 and 3, respectively. optionally , the px_pp strap-in pins can be used to enable this feature. 802.1p-based priority for 802.1p based priority, the ksz8993m will examine the i ngress (incoming) packets to determine whether they are tagged. if tagged, the 3-bits priority field in the vlan tag is retrieved and compared against the priority base value, specified by register 2 bits [6:4]. the priorit y base value is programmable; its default value is 0x4. the following figure illustrates how the 802.1p priori ty field is embedded in the 802.1q vlan tag. preamble da tci 86 6 2 length llc data fcs 2 46-1500 4 1 tagged packet type (8100 for ethernet) 802.1p cfi vlan id bytes bits 16 3 12 802.1q vlan tag 2 sa vpid figure 6. 802.1p priority field format if an ingress packet has an equal or higher priority value t han the "priority base" value, the packet will be placed in the high priority transmit queue if the corresponding transmit queue is split. 802.1p based priority is enabled by bit 5 of registers 16, 32 and 48 for ports 1, 2 and 3, respecti vely. optionally, the px_1pen strap-in pins can be used to enable this feature. the ksz8993m provides the option to insert or remove the priority tagged frame's header at each individual egress port. this header, consisting of the 2 bytes vl an protocol id (vpid) and the 2 bytes tag control information field (tci), is also refer to as the 802.1q vlan tag. tag insertion is enabled by bit 2 of registers 16, 32 and 48 fo r ports 1, 2 and 3, respectively. optionally, the px_tagins strap-in pins can be used to enable this f eature. at the egress port, untagged packets are tagged with the ingress ports default tag. the default tags are programmed in regi ster sets {19,20}, {35,36} and {51,52} for ports 1, 2 and 3, respectively. the ksz8993m will not add tags to already tagged packets. tag removal is enabled by bit 1 of registers 16, 32 and 48 fo r ports 1, 2 and 3, respectively. optionally, the px_tagrm strap-in pins can be used to enable this feat ure. at the egress port, tagged packets will have their 802.1q vlan tags removed. the ksz8993m will not modify untagged packets. the crc is recalculated for both tag insertion and tag removal. 802.1p priority field re-mapping is a qos feature that allows the ksz8993m to set the user priority ceiling at any ingress port. if the ingress packets priority field has a higher priority value than the default tags priority field of the ingress port, the packets priority field is replaced with the default tags priority field. the user priority ceiling is enabled by bit 3 of registers 16, 32 and 48 for ports 1, 2 and 3, respectively. diffserv-based priority diffserv-based priority uses registers 96 to 103. more details are provided at t he beginning of the advanced control registers section. downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 39 m9999-020606 rate limiting support the ksz8993m supports hardware rate limiting independently on the receive side and on the transmit side on a per port basis. rate limiting is supported in both prio rity and non-priority environment. the rate limit starts from 0 kbps and goes up to the line rate in steps of 32 kbps. the ksz8993m uses one second as the rate limiting interval. at the beginning of each interval, the counter is cleared to zero, and the rate limit mechanism starts to count the number of bytes during the interval. on the receive side, if the number of bytes exceeds the programmed limit, t he switch will stop receiving packets on the port until the one second interval expires. flow control can be enabled to prevent packet loss. if the rate limit is programmed greater than or equal to 128 kbps and the byte counter is 8 kbytes below the limit, flow control will be triggered. if the rate limit is programm ed lower than 128 kbps and the byte counter is 2 kbytes below the limit, flow control will also be triggered. on the transmit side, if the numbe r of bytes exceeds the programmed limi t, the switch will stop transmitting packets on the port until the one second interval expires. if priority is enabled, the ksz8993m can be programmed to support different rate limits for high priority packets and low priority packets. configuration interface the ksz8993m can operate as both a managed switch and an unmanaged switch. in unmanaged mode, the ksz8993m is typically programmed using an eeprom . if no eeprom is present, the ksz8993m is configured using its default register settings. some defaults settings are configured via strap-in pin options. the strap-in pins are indicated in the ksz8993m pin description and i/o assignment table. i 2 c master serial bus configuration with an additional i 2 c (2-wire) eeprom, the ksz8993m can perform more advanced swit ch features like broadcast storm protection and rate control without the need of an external processor. for ksz8993m i 2 c master configuration, the eeprom stores the c onfiguration data for regist er 0 to register 109 (as defined in the ksz8993m register map) with the except ion of the read only status registers. after the de- assertion of reset, the ksz8993m will sequentially read in the configuration data for all 110 registers, starting from register 0. the configuration access time (t prgm ) is less than 15 ms, as depicted in the following figure. .... .... .... rst_n scl sda t prgm <15 ms figure 7. ksz8993m eeprom c onfiguration timing diagram the following is a sample procedure for programming the ksz8993m with a pre-configured eeprom: 1. connect the ksz8993m to the eeprom by joining the scl and sda signals of t he respective devices. for the ksz8993m, scl is pin 97 and sda is pin 98. downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 40 m9999-020606 2. enable i 2 c master mode by setting the ksz8993m strap-in pins , ps[1:0] (pins 100 and 101, respectively) to 00. 3. check to ensure that the ksz8993m reset signal input, rs t_n (pin 67), is properly connected to the external reset source at the board level. 4. program the desired confi guration data into the eeprom. 5. place the eeprom on the boar d and power up the board. 6. assert an active-low reset to the rst_n pin of t he ksz8993m. after reset is de-asserted, the ksz8993m will begin reading the configuration data from the eeprom. the ksz8993m will check that the first byte read from the eeprom is 93. if this value is correct, eepro m configuration will continue. if not, eeprom configuration ac cess is denied and all other data sent from the eeprom will be ignored by the ksz8993m. the configuration access time (t prgm ) is less than 15ms. note: for proper operation, check to ensure that the ksz8993m pwrdn input signal (pin 36) is not asserted during the reset operation. the pwrdn input is active low. i 2 c slave serial bus configuration in managed mode, the ksz8993m can be configured as an i 2 c slave device. in this mode, an i 2 c master device (external controller/cpu) has complete programming ac cess to the ksz8993ms 128 registers. programming access includes the global registers, port registers, advanced control registers and indirect access to the static mac table, vlan table, dynamic mac tabl e, and mib counters. the tables and counters are indirectly accessed via registers 110 thru 120. in i 2 c slave mode, the ksz8993m operates like other i 2 c slave devices. addressing the ksz8993ms 8 bit registers is similar to addre ssing atmels at24c02 eeproms memory locations. details of i 2 c read/write operations and related timing information can be found in the at24c02 datasheet. two fixed 8 bits device addresses are used to address the ksz8993m in i 2 c slave mode. one is for read; the other is for write. the addresses are as follow: 1011_1111 1011_1110 the following is a sample procedure for programming the ksz8993m using the i 2 c slave serial bus: 1. enable i 2 c slave mode by setting the ksz8993m strap-in pins ps[1:0] (pins 100 and 101, respectively) to 01. 2. power up the board and assert reset to the ksz8993m. afte r reset, the start switch bit (register 1 bit 0) will be set to 0. 3. configure the desired register se ttings in the ksz8993m, using the i 2 c write operation. 4. read back and verify the register settings in the ksz8993m, using the i 2 c read operation. 5. write a 1 to the start switch bit to start the ksz8993m with the programmed settings. note: the start switch bit cannot be set to 0 to stop the switch after an 1 is written to this bit. thus, it is recommended that all switch configuration settings are prog rammed before the start switch bit is set to 1. some of the configuration settings, such as aging enabl e, auto negotiation enable, force speed and power down can be programmed after the switch has been started. spi slave serial bus configuration in managed mode, the ksz8993m can be configured as a spi slave device. in this mode, a spi master device (external controller/cpu) has complete programming ac cess to the ksz8993ms 128 registers. programming access includes the global registers, port registers, advanced control registers and indirect access to the static mac table, vlan table, dynamic mac table and mib counters. the tables and counters are indirectly accessed via registers 110 thru 120. the ksz8993m supports two standard spi commands: 0000_0011 for data read and 0000_0010 for data write. spi multiple read and multiple write are also support ed by the ksz8993m to expedite register read back and register configuration, respectively. downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 41 m9999-020606 spi multiple read is initiated when the master device continues to drive the ksz8993m spis_n input pin (spi slave select signal) low after a byte (a register) is read. the ksz8993m internal address counter will increment automatically to the next byte (next re gister) after the read. the next byte at the next register address will be shifted out onto the ksz8993m spiq output pin. spi mult iple read will continue until the spi master device terminates it by de-asserting the spis_n signal to the ksz8993m. similarly, spi multiple write is initiated when the ma ster device continues to drive the ksz8993m spis_n input pin low after a byte (a register) is written. the ksz8993m internal address counter will increment automatically to the next byte (next register) after the write. the next byte that is sent from the master device to the ksz8993m sda input pin will be written to the next register addre ss. spi multiple write will continue until the spi master device terminates it by de-assertin g the spis_n signal to the ksz8993m. for both spi multiple read and multiple write, the ksz8993m internal addre ss counter will wrap back to register address zero once the highest register address is reache d. this feature allows all 128 ksz8993m registers to be read, or written with a single spi command and any initial register address. the ksz8993m is capable of supporting a 5mhz spi bus. the following is a sample procedure for programming the ksz8993m using the spi bus: 1. at the board level, connect the ksz8993m pins as follows: ksz8993m pin # ksz8993m signal name external processor signal description 99 spis_n spi slave select 97 scl (spic) spi clock 98 sda (spid) spi data (master output; slave input) 96 spiq spi data (master input; slave output) table 11. ksz8993m spi connections 2. enable spi slave mode by setting t he ksz8993m strap-in pins ps[1:0] (pins 100 and 101, respectively) to 10. 3. power up the board and assert reset to the ksz8993m. after reset, the start switch bit (register 1 bit 0) will be set to 0. 4. configure the desired register settings in the ksz8993 m, using the spi write or multiple write command. 5. read back and verify the register settings in the ksz8993m, using the spi read or multiple read command. 6. write a 1 to the start switch bit to start the ksz8993m with the programmed settings. note: the start switch bit cannot be set to 0 to stop the switch after an 1 is written to this bit. thus, it is recommended that all switch configuration settings are prog rammed before the start switch bit is set to 1. some of the configuration settings, such as aging enabl e, auto negotiation enable, force speed and power down can be programmed after the switch has been started. the following four figures illustrate the spi data cycles for write, read, multiple write and multiple read. the read data is registered out of spiq on the falling edge of spic, and the data input on spid is registered on the rising edge of spic. downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 42 m9999-020606 spiq spic spid spis_n 00000010 x a7 a6 a5 a4 a3 a2 a1 a0 write command write address write data d2 d0 d1 d3 d4 d5 d6 d7 figure 8. spi write data cycle spiq spic spid spis_n 00000011 x a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 read command read address read data figure 9. spi read data cycle spiq spic spid spis_n 00000010 x a7 a6 a5 a4 a3 a2 a1 a0 write command write address byte 1 d2 d0 d1 d3 d4 d5 d6 d7 spiq spic spid spis_n d7 d6 d5 d4 d4 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 byte 2 byte 3 ... byte n d2 d0 d1 d3 d4 d5 d6 d7 figure 10. spi multiple write downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 43 m9999-020606 spiq spic spid spis_n 00000011 x a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 read command read address byte 1 xxxxxxxx xxxxxxx x byte 2 byte 3 byte n x x x x x x x x xxxxxxxx d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 spiq spic spid spis_n figure 11. spi multiple read downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 44 m9999-020606 loopback support the ksz8993m provides loopback support for remote diagno stic of failure. in loopback mode, the speed at both phy ports needs to be set to 100base-tx, and the pri ority buffer reserve bit needs to be set to 48 pre- allocated buffers per output queue. the latter is requir ed to prevent loopback packet drops and is achieved by setting register 4 bit 0 to 1. bit 0 of registers 29 and 45 is used to enable loopback for ports 1 and 2, respectively. alternatively, the mii management register 0, bit 14 can be used to enable loopback. loopback is conducted between the ksz8993ms two phy ports . the loopback path starts at the originating. phy ports receive inputs (rxp/rxm), wraps around at the loopback phy ports pmd/pma, and ends at the originating phy ports transmit outputs (txp/txm). the ksz8993m loopback path is illu strated in the following figure. figure 12. loopback path downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 45 m9999-020606 mii management (miim) registers the miim interface is used to access the mii phy registers defined in this section. the spi, i 2 c, and smi interfaces can also be used to access these registers. the latter three interfaces use a different mapping mechanism than the miim interface. as defined in the ieee 802.3 specificat ion, the phyad are assigned as 0 x1 for phy port 1 and 0x2 for phy port 2. the regad supported are 0,1,2,3,4, and 5. register 0: mii basic control bit name r/w description default reference 15 soft reset ro not supported 0 14 loopback r/w =1, loopback mode =0, normal operation 0 reg. 29, bit 0 reg. 45, bit 0 13 force 100 r/w =1, 100 mbps =0, 10 mbps 0 reg. 28, bit 6 reg. 44, bit 6 12 an enable r/w =1, auto-negotiation enabled =0, auto-negotiation disabled 1 11 power down r/w =1, power down =0, normal operation 0 reg. 29, bit 3 reg. 45, bit 3 10 isolate ro not supported 0 9 restart an r/w =1, restart auto-negotiation =0, normal operation 0 reg. 29, bit 5 reg. 45, bit 5 8 force full duplex r/w =1, full duplex =0, half duplex 0 reg. 28, bit 5 reg. 44, bit 5 7 collision test ro not supported 0 6 reserved ro 0 5 reserved ro 0 4 force mdi r/w =1, force mdi (transmit on rxp / rxm pins) =0, normal operation (transmit on txp / txm pins) 0 reg. 29, bit 1 reg. 45, bit 1 register number description 0x0 basic control register 0x1 basic status register 0x2 physical identifier i 0x3 physical identifier ii 0x4 auto-negotiation advertisement register 0x5 auto-negotiation link partner ability register 0x6 C 0x1f not supported downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 46 m9999-020606 register 0: mii basic control (continued) bit name r/w description default reference 3 disable mdix r/w =1, disable auto mdi-x =0, normal operation 0 reg. 29, bit 2 reg. 45, bit 2 2 disable far end fault r/w =1, disable far end fault detection =0, normal operation 0 reg. 29, bit 4 1 disable transmit r/w =1, disable transmit =0, normal operation 0 reg. 29, bit 6 reg. 45, bit 6 0 disable led r/w =1, disable led =0, normal operation 0 reg. 29, bit 7 reg. 45, bit 7 register 1: mii basic status bit name r/w description default reference 15 t4 capable ro =0, not 100 base-t4 capable 0 14 100 full capable ro =1, 100base-tx full duplex capable =0, not capable of 100base-tx full duplex 1 always 1 13 100 half capable ro =1, 100base-tx half duplex capable =0, not 100base-tx half duplex capable 1 always 1 12 10 full capable ro =1, 10base-t full duplex capable =0, not 10base-t full duplex capable 1 always 1 11 10 half capable ro =1, 10base-t half duplex capable =0, not 10base-t half duplex capable 1 always 1 10-7 reserved ro 0 6 preamble suppressed ro not supported 0 5 an complete ro =1, auto-negotiation complete =0, auto-negotiation not completed 0 reg. 30, bit 6 reg. 46, bit 6 4 far end fault ro =1, far end fault detected =0, no far end fault detected 0 reg. 31, bit 0 3 an capable ro =1, auto-negotiation capable =0, not auto-negotiation capable 1 reg. 28, bit 7 reg. 44, bit 7 2 link status ro =1, link is up =0, link is down 0 reg. 30, bit 5 reg. 46, bit 5 1 jabber test ro not supported 0 0 extended capable ro =0, not extended register capable 0 register 2: phyid high bit name r/w description default 15-0 phyid high ro high order phyid bits 0x0022 register 3: phyid low bit name r/w description default 15-0 phyid low ro low order phyid bits 0x1430 downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 47 m9999-020606 register 4: auto-negotiation advertisement ability bit name r/w description default reference 15 next page ro not supported 0 14 reserved ro 0 13 remote fault ro not supported 0 12-11 reserved ro 0 10 pause r/w =1, advertise pause ability =0, do not advertise pause ability 1 reg. 28, bit 4 reg. 44, bit 4 9 reserved r/w 0 8 adv 100 full r/w =1, advertise 100 full duplex ability =0, do not advertise 100 full duplex ability 1 reg. 28, bit 3 reg. 44, bit 3 7 adv 100 half r/w =1, advertise 100 half duplex ability =0, do not advertise 100 half duplex ability 1 reg. 28, bit 2 reg. 44, bit 2 6 adv 10 full r/w =1, advertise 10 full duplex ability =0, do not advertise 10 full duplex ability 1 reg. 28, bit 1 reg. 44, bit 1 5 adv 10 half r/w =1, advertise 10 half duplex ability =0, do not advertise 10 half duplex ability 1 reg. 28, bit 0 reg. 44, bit 0 4-0 selector field ro 802.3 00001 register 5: auto-negotiation link partner ability bit name r/w description default reference 15 next page ro not supported 0 14 lp ack ro not supported 0 13 remote fault ro not supported 0 12-11 reserved ro 0 10 pause ro link partner pause capability 0 reg. 30, bit 4 reg. 46, bit 4 9 reserved ro 0 8 adv 100 full ro link partner 100 full capability 0 reg. 30, bit 3 reg. 46, bit 3 7 adv 100 half ro link partner 100 half capability 0 reg. 30, bit 2 reg. 46, bit 2 6 adv 10 full ro link partner 10 full capability 0 reg. 30, bit 1 reg. 46, bit 1 5 adv 10 half ro link partner 10 half capability 0 reg. 30, bit 0 reg. 46, bit 0 4-0 reserved ro 00000 downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 48 m9999-020606 register map: switch & phy (8 bit registers) global registers register (decimal) register (hex0 description 0-1 0x00-0x01 chip id registers 2-11 0x02-0x0b global control registers 12 0x0c reserved register 13-15 0x0d-0x0f user defined registers port registers register (decimal) register (hex0 description 16-29 0x10-0x1d port 1 control registers, including mii phy registers 30-31 0x1e-0x1f port 1 status regi sters, including mii phy registers 32-45 0x20-0x2d port 2 control registers, including mii phy registers 46-47 0x2e-0x2f port 2 status regi sters, including mii phy registers 48-61 0x30-0x3d port 3 control registers, including mii phy registers 62-63 0x3e-0x3f port 3 status regi sters, including mii phy registers 64-95 0x40-0x5f reserved advanced control registers register (decimal) register (hex0 description 96-103 0x60-0x67 tos priority control registers 104-109 0x68-0x6d switch engines mac address registers 110-111 0x6e-0x6f indirect access control registers 112-120 0x70-0x78 indirect data registers 121-122 0x79-0x7a digital te sting status registers 123-124 0x7b-0x7c digital testing control registers 125-126 0x7d-0x7e analog testing control registers 127 0x7f analog testing status register global registers register 0 (0x00): chip id0 bit name r/w description default 7-0 family id ro chip family 0x93 downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 49 m9999-020606 register 1 (0x01): chip id1 / start switch bit name r/w description default 7-4 chip id ro 0x0 is assigned to m series. (93m) 0x0 3-1 revision id ro revision id - 0 start switch rw = 1, start the chip when external pins (ps1, ps0) = (0,1) or (1,0) or (1,1). note: in (ps1, ps0) = (0, 0) mode, the chip will start automatically after trying to read the external eeprom. if eeprom does not exist, the chip will use pin strapping and default values for all internal registers. if eeprom is present, the contents in the eeprom will be checked. the switch will check: (1) register 0 = 0x93, (2) register 1 bits [7:4] = 0x0. if this check is ok, the contents in the eeprom will override chip registers default values. = 0, chip will not star t when external pins (ps1, ps0) = (0,1) or (1,0) or (1,1). - register 2 (0x02): global control 0 bit name r/w description default 7 new back-off enable r/w new back-off algorithm designed for unh 1 = enable 0 = disable 0x0 6-4 802.1p base priority r/w used to classify priority for incoming 802.1q packets. user priority is compared against this value. >= : classified as high priority < : classified as low priority 0x4 3 pass flow control packet r/w = 1, switch will not filter 802.1x flow control packets 0x0 2 buffer share mode r/w = 1, buffer pool is shared by all ports. a port can use more buffers when other ports are not busy. = 0, a port is only allowed to use 1/3 of the buffer pool. 0x1 1 reserved r/w reserved 0 0 link change age r/w = 1, link change from link to no link will cause fast aging (<800us) to age address table faster. after an age cycle is complete, the age logic will return to normal aging (about 200 sec). note: if any port is unplugged, all addresses will be automatically aged out. 0 downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 50 m9999-020606 register 3 (0x03): global control 1 bit name r/w description default 7 pass all frames r/w = 1, switch all packets including bad ones. used solely for debugging purposes. works in conjunction with sniffer mode only. 0 6 repeater mode r/w 0 = normal mode 1 = repeater mode (half duplex hub mode) 0 5 ieee 802.3x transmit direction flow control enable r/w = 1, will enable transmit di rection flow control feature. = 0, will not enable transmit direction flow control feature. 1 4 ieee 802.3x receive direction flow control enable r/w = 1, will enable receive di rection flow control feature. = 0, will not enable receive direction flow control feature. 1 3 frame length field check r/w 1 = will check frame length field in the ieee packets. if the actual length does not match, the packet will be dropped (for length/type field < 1500). 0 2 aging enable r/w 1 = enable age function in the chip 0 = disable age function in the chip 1 1 fast age enable r/w 1 = turn on fast age (800us) 0 0 aggressive back off enable r/w 1 = enable more aggressive back off algorithm in half duplex mode to enhance performance. this is not an ieee standard. smac (pin 69) value during reset. register 4 (0x04): global control 2 bit name r/w description default 7 unicast port- vlan mismatch discard r/w this feature is used for port-vlan (described in reg. 17, reg. 33, ) = 1, all packets can not cross vlan boundary = 0, unicast packets (excluding unkown/multicast/broadcast) can cross vlan boundary note: port mirroring is not supported if this bit is set to 0. 1 6 multicast storm protection disable r/w = 1, broadcast storm protection does not include multicast packets. only da = ffffffffffff packets will be regulated. = 0, broadcast storm protection includes da = ffffffffffff and da[40] = 1 packets. 1 5 back pressure mode r/w = 1, carrier sense based backpressure is selected = 0, collision based backpressure is selected 1 downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 51 m9999-020606 register 4 (0x04): global control 2 (continued) bit name r/w description default 4 flow control and back pressure fair mode r/w = 1, fair mode is selected. in this mode, if a flow control port and a non-flow control port talk to the same destination port, packets from the non-flow control port may be dropped. this is to prevent the flow control port from being flow controlled for an extended period of time. = 0, in this mode, if a flow control port and a non-flow control port talk to the sa me destination port, the flow control port will be flow controlled. this may not be fair to the flow control port. 1 3 no excessive collision drop r/w = 1, the switch will not drop packets when 16 or more collisions occur. = 0, the switch will drop packets when 16 or more collisions occur. smac (pin 69) value during reset. 2 huge packet support r/w = 1, will accept packet sizes up to 1916 bytes (inclusive). this bit setting will override setting from bit 1 of the same register. = 0, the max packet size will be determined by bit 1 of this register. 0 1 legal maximum packet size check enable r/w = 0, will accept packet sizes up to 1536 bytes (inclusive). = 1, 1522 bytes for tagged packets, 1518 bytes for untagged packets. any packets larger than the specified value will be dropped. smrxd0 (pin 85) value during reset. 0 priority buffer reserve r/w = 1, each output queue is pre-allocated 48 buffers, used exclusively for high priority packets. it is recommended to enable this when priority queue feature is turned on. = 0, no reserved buffers for high priority packets. 1 register 5 (0x05): global control 3 bit name r/w description default 7 802.1q vlan enable r/w = 1, 802.1q vlan mode is turned on. vlan table needs to set up before the operation. = 0, 802.1q vlan is disabled. 0 6 igmp snoop enable on switch mii interface r/w =1, igmp snoop is enabled. all the igmp packets will be forwarded to the switch mii port. =0, igmp snoop is disabled. 0 5 reserved r/w 0 4 reserved r/w 0 3-2 priority scheme select r/w 00 = always deliver high priority packets first 01 = deliver high/low packets at ratio 10/1 10 = deliver high/low packets at ratio 5/1 11 = deliver high/low packets at ratio 2/1 00 1 reserved r/w 0 downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 52 m9999-020606 register 5 (0x05): global control 3 (continued) bit name r/w description default 0 sniff mode select r./w = 1, will do rx and tx sniff (both source port and destination port need to match) = 0, will do rx or tx sniff (either source port or destination port needs to match). this is the mode used to implement rx only sniff. 0 register 6 (0x06): global control 4 bit name r/w description default 7 reserved r/w 0 6 switch mii half- duplex mode r/w = 1, enable mii interface half-duplex mode. = 0, enable mii interface full-duplex mode. pin smrxd2 strap option. pull-down(0): full-duplex mode pull-up(1): half-duplex mode note: smrxd2 has internal pull- down. 5 switch mii flow control enable r/w = 1, enable full-duplex flow control on switch mii interface. = 0, disable full-duplex flow control on switch mii interface. pin smrxd3 strap option. pull-down(0): disable flow control pull- up(1): enable flow control note: smrxd3 has internal pull- down. 4 switch mii 10bt r/w = 1, the switch interface is in 10mbps mode = 0, the switch interface is in 100mbps mode pin smrxd1 strap option. pull C down(0): enable 100mbps pull-up(1): enable 10mpbs note: smrxd1 has internal pull- down. downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 53 m9999-020606 register 6 (0x06): global control 4 (continued) bit name r/w description default 3 null vid replacement r/w = 1, will replace null vid with port vid(12 bits) = 0, no replacement for null vid 0 2-0 broadcast storm protection rate bit [10:8] r/w this register along with t he next register determines how many 64 byte blocks of packet data allowed on an input port in a preset period. the period is 50ms for 100bt or 500ms for 10bt. the default is 1%. 000 register 7 (0x07): global control 5 bit name r/w description default 7-0 broadcast storm protection rate (1) bit [7:0] r/w this register along with the previous register determines how many 64 byte blocks of packet data are allowed on an input port in a preset period. the period is 67ms for 100bt or 500ms for 10bt. the default is 1%. 0x63 note: rate: 148,800 frames/sec * 67 ms/interval * 1% = 99 frames/interval (approx.) = 0x63 register 8 (0x08): global control 6 bit name r/w description default 7-0 factory testing r/w reserved 0x4e register 9 (0x09): global control 7 bit name r/w description default 7-0 factory testing r/w reserved 0x24 register 10 (0x0a): global control 8 bit name r/w description default 7-0 factory testing r/w reserved 0x24 register 11 (0x0b): global control 9 bit name r/w description default 7 reserved reserved 0 6 phy power save r/w = 1, enable phy power save mode = 0, disable phy power save mode 0 5 reserved r/w reserved 0 4 reserved rw testing mode, must be 0 0 3 reserved r/w reserved 1 downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 54 m9999-020606 register 11 (0x0b): global control 9 (continued) bit name r/w description default 2 reserved r/w reserved 0 1 led mode r/w this register bit sets the ledsel0 selection only. ledsel1 is set via strap-in pin. port x led indicators, defined as below: [ledsel1, ledsel0] [0, 0] [0, 1] pxled3 ------ ------ pxled2 link/act 100link/act pxled1 full_dpx/col 10link/act pxled0 speed full_dpx [ledsel1, ledsel0] [1, 0] [1, 1] pxled3 act ------ pxled2 link ------ pxled1 full_dpx/col ------ pxled0 speed ------ notes: ledsel0 is external strap-in pin #70. ledsel1 is external strap-in pin #23. ledsel0 pin value during reset. 0 special tpid mode r/w used for direct mode forwarding from port 3. see description in spanning tree functional description. 0 = disable 1 = enable 0 register 12 (0x0c): reserved register bit name r/w description default 7-0 reserved reserved 0x00 register 13 (0x0d): user defined register 1 bit name r/w description default 7-0 udr1 r/w 0x00 register 14 (0x0e): user defined register 2 bit name r/w description default 7-0 udr2 r/w 0x00 register 15 (0x0f): user defined register 3 bit name r/w description default 7-0 udr3 r/w 0x00 downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 55 m9999-020606 port registers the following registers are used to enable features that are assigned on a per port basis. the register bit assignments are the same for all ports, but the addres s for each port is different, as indicated. register 16 (0x10): port 1 control 0 register 32 (0x20): port 2 control 0 register 48 (0x30): port 3 control 0 bit name r/w description default 7 broadcast storm protection enable r/w = 1, enable broadcast storm protection for ingress packets on the port = 0, disable broadcast storm protection 0 6 diffserv priority classification enable r/w = 1, enable diffserv priority classification for ingress packets on port = 0, disable diffserv function 0 5 802.1p priority classification enable r/w = 1, enable 802.1p priority classification for ingress packets on port = 0, disable 802.1p pin value during reset: p1_1pen (port 1) p2_1pen (port 2) p3_1pen (port 3) 4 port-based priority classification enable r/w = 1, ingress packets on the port will be classified as high priority if diffserv or 802.1p classification is not enabled or fails to classify. = 0, ingress packets on port will be classified as low priority if diffserv or 802.1p classification is not enabled or fails to classify. note: diffserv, 802.1p and port priority can be enabled at the same time. the ored result of 802.1p and dscp overwrites the port priority. pin value during reset: p1_pp (port 1) p2_pp (port 2) p3_pp (port 3) 3 user priority ceiling r/w = 1, if the packets user priority field is greater than the user priority fiel d in the port default tag register, replace the packets user priority field with the user priority field in the port default tag register. = 0, do not compare and replace the packets user priority field 0 2 tag insertion r/w = 1, when packets are output on the port, the switch will add 802.1p/q tags to packets without 802.1p/q tags when received. the switch will not add tags to packets already tagged. the tag inserted is the ingress ports port vid. = 0, disable tag insertion pin value during reset: p1_tagins (port 1) p2_tagins (port 2) p3_tagins (port 3) downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 56 m9999-020606 register 16 (0x10): port 1 control 0 register 32 (0x20): port 2 control 0 register 48 (0x30): port 3 control 0 (continued) bit name r/w description default 1 tag removal r/w = 1, when packets are output on the port, the switch will remove 802.1p/q tags from packets with 802.1p/q tags when received. the switch will not modify packets received without tags. = 0, disable tag removal pin value during reset: p1_tagrm (port 1) p2_tagrm (port 2) p3_tagrm (port 3) 0 priority enable r/w = 1, the port output queue is split into high and low priority queues. = 0, single output queue on the port. there is no priority differentiation even though packets are classified into high or low priority. pin value during reset: p1_txq2 (port 1) p2_txq2 (port 2) p3_txq2 (port 3) register 17 (0x11): port 1 control 1 register 33 (0x21): port 2 control 1 register 49 (0x31): port 3 control 1 bit name r/w description default 7 sniffer port r/w = 1, port is designated as sniffer port and will transmit packets that are monitored. = 0, port is a normal port 0 6 receive sniff r/w = 1, all the packets received on the port will be marked as monitored packets and forwarded to the designated sniffer port = 0, no receive monitoring 0 5 transmit sniff r/w = 1, all the packets transmitted on the port will be marked as monitored packets and forwarded to the designated sniffer port = 0, no transmit monitoring 0 4 double tag r/w = 1, all packets will be tagged with port default tag of ingress port regar dless of the original packets are tagged or not = 0, do not double tagged on all packets 0x0 3 reserved r/w 0x0 2-0 port vlan membership r/w define the ports egress port vlan membership. bit 2 stands for port 3, bit 1 for port 2 bit 0 for port 1. the port can only communicate within the membership. a 1 includes a port in the membership, a 0 excludes a port from membership. pin value during reset: for port 1, (pv13, pv12, 1) for port 2, (pv23, 1, pv21) for port 3, (1, pv32, pv31) downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 57 m9999-020606 register 18 (0x12): port 1 control 2 register 34 (0x22): port 2 control 2 register 50 (0x32): port 3 control 2 bit name r/w description default 7 reserved reserved 0 6 ingress vlan filtering r/w = 1, the switch will discard packets whose vid port membership in vlan table bits [18:16] does not include the ingress port. = 0, no ingress vlan filtering. 0 5 discard non pvid packets r/w = 1, the switch will discard packets whose vid does not match ingress port default vid. = 0, no packets will be discarded 0 4 force flow control r/w = 1, will always enable flow control on the port, regardless of an result. = 0, the flow control is enabled based on an result. pin value during reset: for port 1, p1ffc pin for port 2, p2ffc pin for port 3, this bit has no meaning. flow control is controlled by reg. 6, bit 5. 3 back pressure enable r/w = 1, enable ports half duplex back pressure = 0, disable ports half duplex back pressure. pin value during reset: bpen pin 2 transmit enable r/w = 1, enable packet transmission on the port = 0, disable packet transmission on the port 1 1 receive enable r/w = 1, enable packet reception on the port = 0, disable packet reception on the port 1 0 learning disable r/w = 1, disable switch address learning capability = 0, enable switch address learning 0 note: bits [2:0] are used for spanning tree support (see page 33). register 19 (0x13): port 1 control 3 register 35 (0x23): port 2 control 3 register 51 (0x33): port 3 control 3 bit name r/w description default 7-0 default tag [15:8] r/w ports default tag, containing 7-5 : user priority bits 4 : cfi bit 3-0 : vid[11:8] 0x00 downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 58 m9999-020606 register 20 (0x14): port 1 control 4 register 36 (0x24): port 2 control 4 register 52 (0x34): port 3 control 4 bit name r/w description default 7-0 default tag [7:0] r/w ports default tag, containing 7-0: vid[7:0] 0x01 note: registers 19 and 20 (and those corresponding to other ports) serve two purposes: 1. associated with the ingress unt agged packets, and used for egress tagging. 2. default vid for the ingress untagged or null- vid-tagged packets, and used for address lookup. register 21 (0x15): port 1 control 5 register 37 (0x25): port 2 control 5 register 53 (0x35): port 3 control 5 bit name r/w description default 7-0 transmit high priority rate control [7:0] r/w this register along with port control 7, bits [3:0] form a 12-bits field to determine how many 32kbps high priority blocks can be transmitted in a unit of 4kbytes in a one second period). 0x00 register 22 (0x16): port 1 control 6 register 38 (0x26): port 2 control 6 register 54 (0x36): port 3 control 6 bit name r/w description default 7-0 transmit low priority rate control [7:0] r/w this register along with port control 7, bits [7:4] form a 12-bits field to determine how many 32kbps low priority blocks can be transmitted in a unit of 4 kbytes in a one second period). 0x00 register 23 (0x17): port 1 control 7 register 39 (0x27): port 2 control 7 register 55 (0x37): port 3 control 7 bit name r/w description default 7-4 transmit low priority rate control [11:8] r/w these bits along with port control 6, bits [7:0] form a 12-bits field to determine how many 32kbps low priority blocks can be transmitted in a unit of 4kbytes in a one second period). 0x0 3-0 transmit high priority rate control [11:8] r/w these bits along with port control 5, bits [7:0] form a 12-bits field to determine how many 32kbps high priority blocks can be transmitted (in a unit of 4kbytes in a one second period). 0x0 register 24 (0x18): port 1 control 8 register 40 (0x28): port 2 control 8 register 56 (0x38): port 3 control 8 bit name r/w description default 7-0 receive high priority rate control [7:0] r/w this register along with port control 10, bits [3:0] form a 12-bits field to determine how many 32kbps high priority blocks can be received in a unit of 4kbytes in a one second period). 0x00 downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 59 m9999-020606 register 25 (0x19): port 1 control 9 register 41 (0x29): port 2 control 9 register 57 (0x39): port 3 control 9 bit name r/w description default 7-0 receive low priority rate control [7:0] r/w this register along with port control 10, bits [7:4] form a 12-bits field to determine how many 32kbps low priority blocks can be received (in a unit of 4kbytes in a one second period). 0x00 register 26 (0x1a): port 1 control 10 register 42 (0x2a): port 2 control 10 register 58 (0x3a): port 3 control 10 bit name r/w description default 7-4 receive low priority rate control [11:8] r/w these bits along with port control 9, bits [7:0] form a 12-bits field to determine how many 32kbps low priority blocks can be received (in a unit of 4kbytes in a one second period). 0x0 3-0 receive high priority rate control [11:8] r/w these bits along with port control 8, bits [7:0] form a 12-bits field to determine how many 32kbps high priority blocks can be received (in a unit of 4kbytes in a one second period). 0x0 register 27 (0x1b): port 1 control 11 register 43 (0x2b): port 2 control 11 register 59 (0x3b): port 3 control 11 bit name r/w description default 7 receive differential priority rate control r/w = 1, if bit 6 is also 1 this will enable receive rate control for this port on low priority packets at the low priority rate. if bit 5 is also 1, this will enable receive rate control on high priority packets at the high priority rate. = 0, receive rate control will be based on the low priority rate for all packets on this port. 0 6 low priority receive rate control enable r/w = 1, enable ports low priority receive rate control feature = 0, disable ports low priority receive rate control 0 5 high priority receive rate control enable r/w = 1, if bit 7 is also 1 this will enable the ports high priority receive rate control feature. if bit 7 is a 0 and bit 6 is a 1, all receive packets on this port will be rate controlled at the low priority rate. = 0, disable ports high priority receive rate control feature 0 4 low priority receive rate flow control enable r/w = 1, flow control may be asserted if the ports low priority receive ra te is exceeded. = 0, flow control is not asserted if the ports low priority receive ra te is exceeded. 0 downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 60 m9999-020606 register 27 (0x1b): port 1 control 11 register 43 (0x2b): port 2 control 11 register 59 (0x3b): port 3 control 11 (continued bit name r/w description default 3 high priority receive rate flow control enable r/w = 1, flow control may be asserted if the ports high priority receive rate is exceeded. (to use this, differential receive rate control must be on.) = 0, flow control is not asserted if the ports high priority receive ra te is exceeded. 0 2 transmit differential priority rate control r/w = 1, will do transmit rate control on both high and low priority packets based on the rate counters defined by the high and low priority packets respectively. = 0, will do transmit rate control on any packets. the rate counters defined in low priority will be used. 0 1 low priority transmit rate control enable r/w 1, enable the ports low priority transmit rate control feature = 0, disable the ports low priority transmit rate control feature 0 0 high priority transmit rate control enable r/w = 1, enable the ports high priority transmit rate control feature = 0, disable the ports high priority transmit rate control feature 0 note: port control 12 and 13, and port status 0 contents can also be accessed with the miim (mdc/mdio) interface via the standard miim registers. register 28 (0x1c): port 1 control 12 register 44 (0x2c): port 2 control 12 register 60 (0x3c): reserved, not applied to port 3 bit name r/w description default 7 auto negotiation enable r/w = 0, disable auto negotiation, speed and duplex are decided by bit 6 and 5 of the same register. = 1, auto negotiation is on for port 1, p1anen pin value during reset. for port 2, p2anen pin value during reset 6 force speed r/w = 1, forced 100bt if an is disabled (bit 7) = 0, forced 10bt if an is disabled (bit 7) for port 1, p1spd pin value during reset. for port 2, p2spd pin value during reset. downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 61 m9999-020606 register 28 (0x1c): port 1 control 12 register 44 (0x2c): port 2 control 12 register 60 (0x3c): reserved, not applied to port 3 (continued) bit name r/w description default 5 force duplex r/w = 1, forced full duplex if (1) an is disabled or (2) an is enabled but failed. = 0, forced half duplex if (1) an is disabled or (2) an is enabled but failed. for port 1, p1dpx pin value during reset. for port 2, p2dpx pin value during reset. 4 advertised flow control capability r/w = 1, advertise flow control (pause) capability = 0, suppress flow control (pause) capability from transmission to link partner advfc pin value during reset. 3 advertised 100bt full- duplex capability r/w = 1, advertise 100bt full-duplex capability = 0, suppress 100bt full-duplex capability from transmission to link partner 1 2 advertised 100bt half- duplex capability r/w = 1, advertise 100bt half-duplex capability = 0, suppress 100bt half-duplex capability from transmission to link partner 1 1 advertised 10bt full- duplex capability r/w = 1, advertise 10bt full-duplex capability = 0, suppress 10bt full-duplex capability from transmission to link partner 1 0 advertised 10bt half- duplex capability r/w = 1, advertise 10bt half-duplex capability = 0, suppress 10bt half-duplex capability from transmission to link partner 1 register 29 (0x1d): port 1 control 13 register 45 (0x2d): port 2 control 13 register 61 (0x3d): reserved, not applied to port 3 bit name r/w description default 7 led off r/w = 1, turn off all ports leds (ledx_3, ledx_2, ledx_1, ledx_0, where x is the port number). these pins will be driven high if this bit is set to one. = 0, normal operation 0 6 txids r/w = 1, disable ports transmitter = 0, normal operation 0 5 restart an r/w = 1, restart auto-negotiation = 0, normal operation 0 downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 62 m9999-020606 register 29 (0x1d): port 1 control 13 register 45 (0x2d): port 2 control 13 register 61 (0x3d): reserved, not applied to port 3 (continued) bit name r/w description default 4 disable far end fault r/w = 1, disable far end fault detection and pattern transmission. = 0, enable far end fault detection and pattern transmission 0 note: only port 1 supports fiber. this bit is applicable to port 1 only. 3 power-down r/w = 1, power-down = 0, normal operation 0 2 disable auto mdi/mdi-x r/w = 1, disable auto mdi/mdi-x function = 0, enable auto mdi/mdi-x function 0 for port 2, p2mdix disable pin value during reset. 1 force mdi-x r/w if auto mdi/mdi-x is disabled, = 1, force phy into mdi mode (transmit on rxp/rxm pins) = 0, force phy into mdi-x mode (transmit on txp/txm pins) 0 for port 2, p2mdix pin value during reset. 0 loopback r/w = 1, perform loopback, as indicated: port 1 loopback (reg. 29, bit 0 = 1) start: rxp2/rxm2 (port 2) loopback: pmd/pma of port 1s phy end: txp2/txm2 (port 2) port 2 loopback (reg. 45, bit 0 1) start: rxp1/rxm1 (port 1) loopback: pmd/pma of port 2s phy end: txp1/txm1 (port 1) = 0, normal operation 0 register 30 (0x1e): port 1 status 0 register 46 (0x2e): port 2 status 0 register 62 (0x3e): reserved, not applied to port 3 bit name r/w description default 7 mdi-x status ro = 1, mdi-x = 0, mdi 0 6 an done ro = 1, an done = 0, an not done 0 5 link good ro = 1, link good = 0, link not good 4 partner flow control capability ro = 1, link partner flow control (pause) capable = 0, link partner not flow control (pause) capable downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 63 m9999-020606 register 30 (0x1e): port 1 status 0 register 46 (0x2e): port 2 status 0 register 62 (0x3e): reserved, not applied to port 3 (continued) bit name r/w description default 3 partner 100bt full-duplex capability ro = 1, link partner 100bt full-duplex capable = 0, link partner not 100bt full-duplex capable 0 2 partner 100bt half-duplex capability ro = 1, link partner 100bt half-duplex capable = 0, link partner not 100bt half-duplex capable 0 1 partner 10bt full-duplex capability ro = 1, link partner 10bt full-duplex capable = 0, link partner not 10bt full-duplex capable 0 0 partner 10bt half-duplex capability ro = 1, link partner 10bt half-duplex capable = 0, link partner not 10bt half-duplex capable 0 register 31 (0x1f): port 1 status 1 register 47 (0x2f): port 2 status 1 register 63 (0x3f): port 3 status 1 bit name r/w description default 7 reserved ro 0 6-5 reserved ro 00 4 receive flow control enable ro 1 = receive flow control feature is active 0 = receive flow control feature is inactive 0 3 transmit flow control enable ro 1 = transmit flow control feature is active 0 = transmit flow control feature is inactive 0 2 operation speed ro 1 = link speed is 100mbps 0 = link speed is 10mbps 0 1 operation duplex ro 1 = link duplex is full 0 = link duplex is half 0 0 far end fault ro = 1, fa r end fault status detected = 0, no far end fault status detected 0 note: only port 1 supports fiber; this bit is applicable to port 1 only. downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 64 m9999-020606 advanced control registers the ipv4 tos priority control registers implement a fully decoded 64 bit differentiated services code point (dscp) register used to determine priority from the 6 bit tos fiel d in the ip header. the most significant 6 bits of the tos field are fully decoded into 64 possibilities, and the si ngular code that results is compared against the corresponding bit in the dscp register. f the register bit is a 1, the priority is high; if it is a 0, the priority is low. register 96 (0x60): tos priority control register 0 bit name r/w description default 7-0 dscp[63:56] r/w 0000_0000 register 97 (0x61): tos priority control register 1 bit name r/w description default 7-0 dscp[55:48] r/w 0000_0000 register 98 (0x62): tos priority control register 2 bit name r/w description default 7-0 dscp[47:40] r/w 0000_0000 register 99 (0x63): tos priority control register 3 bit name r/w description default 7-0 dscp[39:32] r/w 0000_0000 register 100 (0x64): tos priority control register 4 bit name r/w description default 7-0 dscp[31:24] r/w 0000_0000 register 101 (0x65): tos priority control register 5 bit name r/w description default 7-0 dscp[23:16] r/w 0000_0000 register 102 (0x66): tos priority control register 6 bit name r/w description default 7-0 dscp[15:8] r/w 0000_0000 register 103 (0x67): tos priority control register 7 bit name r/w description default 7-0 dscp[7:0] r/w 0000_0000 downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 65 m9999-020606 registers 104 to 109 registers 104 to 109 define the switching engines mac address. this 48-bit address is used as the sa for mac pause control frames. register 104 (0x68): mac address register 0 bit name r/w description default 7-0 maca[47:40] r/w 0x00 register 105 (0x69): mac address register 1 bit name r/w description default 7-0 maca[39:32] r/w 0x10 register 106 (0x6a): mac address register 2 bit name r/w description default 7-0 maca[31:24] r/w 0xa1 register 107 (0x6b): mac address register 3 bit name r/w description default 7-0 maca[23:16] r/w 0xff register 108 (0x6c): mac address register 4 bit name r/w description default 7-0 maca[15:8] r/w 0xff register 109 (0x6d): mac address register 5 bit name r/w description default 7-0 maca[7:0] r/w 0xff downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 66 m9999-020606 register 110 and 111 use registers 110 and 111 to read or write data to the st atic mac address table, vlan table, dynamic address table, or the mib counters. register 110 (0x6e): indirect access control 0 bit name r/w description default 7-5 reserved r/w reserved 000 4 read high write low r/w = 1, read cycle = 0, write cycle 0 3-2 table select r/w 00 = stat ic mac address table selected 01 = vlan table selected 10 = dynamic address table selected 11 = mib counter selected 00 1-0 indirect address high r/w bit 9-8 of indirect address 00 register 111 (0x6f): indirect access control 1 bit name r/w description default 7-0 indirect address low r/w bit 7-0 of indirect address 0000_0000 note: write to register 111 will actually trigger a command. read or write access is determined by register 110 bit 4. register 112 (0x70): indirect data register 8 bit name r/w description default 68-64 indirect data r/w bit 68-64 of indirect data 0_0000 register 113 (0x71): indirect data register 7 bit name r/w description default 63-56 indirect data r/w bit 63- 56 of indirect data 0000_0000 register 114 (0x72): indirect data register 6 bit name r/w description default 55-48 indirect data r/w bit 55- 48 of indirect data 0000_0000 register 115 (0x73): indirect data register 5 bit name r/w description default 47-40 indirect data r/w bit 47- 40 of indirect data 0000_0000 register 116 (0x74): indirect data register 4 bit name r/w description default 39-32 indirect data r/w bit 39- 32 of indirect data 0000_0000 downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 67 m9999-020606 register 117 (0x75): indirect data register 3 bit name r/w description default 31-24 indirect data r/w bit of 31-24 of indirect data 0000_0000 register 118 (0x76): indirect data register 2 bit name r/w description default 23-16 indirect data r/w bit 23- 16 of indirect data 0000_0000 register 119 (0x77): indirect data register 1 bit name r/w description default 15-8 indirect data r/w bit 15- 8 of indirect data 0000_0000 register 120 (0x78): indirect data register 0 bit name r/w description default 7-0 indirect data r/w bit 7- 0 of indirect data 0000_0000 registers 121 to 127 registers 121 to 127 are reserved. static mac address table the ksz8993m has both a static and a dynamic mac address table. when a destination address (da) lookup is requested, both tables are searched to make a packet forwarding decision. when a sa lookup is requested, only the dynamic table is searched for aging, migration and l earning purposes. the static da lookup result will have precedence over the dynamic da lookup result. if there is a da match in both tables, the result from the static table will be used. the static table c an be accessed and controlled by an external processor via the smi, spi and i 2 c interfaces. the external processor performs all addition, modification and deletion of static table entries. these entries in the static table will not be aged out by the ksz8993m. bit name r/w description default 57-54 fid r/w filter vlan id, representing one of the 16 active vlans 0000 53 use fid r/w = 1, use (fid+mac) to look up in static table = 0, use mac only to look up in static table 0 52 override r/w = 1, override port setting transmit enable=0 or receive enable=0 setting = 0, no override 0 51 valid r/w = 1, this entry is valid, the lookup result will be used = 0, this entry is not valid 0 table 12. format of static mac table (8 entries) downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 68 m9999-020606 bit name r/w description default 50-48 forwarding ports r/w these 3 bits control the forwarding port(s): 001, forward to port 1 010, forward to port 2 100, forward to port 3 011, forward to port 1 and port 2 110, forward to port 2 and port 3 101, forward to port 1 and port 3 111, broadcasting (excluding the ingress port) 000 47-0 mac address r/w 48 bits mac address 0x0000_0000_0000 table 12. format of static mac table (8 entries) (continued) examples: 1. static address table read (read the 2 nd entry) write to reg. 110 with 0x10 (read static table selected) write to reg. 111 with 0x01 (trigger the read operation) then, read reg. 113 (57-56) read reg. 114 (55-48) read reg. 115 (47-40) read reg. 116 (39-32) read reg. 117 (31-24) read reg. 118 (23-16) read reg. 119 (15-8) read reg. 120 (7-0) 2. static address table write (write the 8 th entry) write reg. 113 (57-56) write reg. 114 (55-48) write reg. 115 (47-40) write reg. 116 (39-32) write reg. 117 (31-24) write reg. 118 (23-16) write reg. 119 (15-8) write reg. 120 (7-0) write to reg. 110 with 0x00 (write static table selected) write to reg. 111 with 0x07 (trigger the write operation) vlan table vlan table is used to do vlan table lookup. if 802.1q vl an mode is enabled (register 5, bit 7 = 1), this table will be used to retrieve the vlan inform ation that is associated with the ingr ess packet. this info rmation includes fid (filter id), vid (vlan id), and vlan memb ership as described in the following table. downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 69 m9999-020606 bit name r/w description default 19 valid r/w = 1, the entry is valid = 0, entry is invalid 1 18-16 membership r/w specify which ports are members of the vlan. if a da lookup fails (no match in both static and dynamic tables), then the packet associated with this vlan will be forwarded to ports specified in this field. for example, 101 means port 3 and 1 are in this vlan. 111 15-12 fid r/w filter id. ksz8993m supports 16 active vlans represented by these four bit fields. fid is the mapped id. if 802.1q vlan is enabled, the lookup will be based on fid+da and fid+sa. 0x0 11-0 vid r/w ieee 802.1q 12 bits vlan id 0x001 table 13. format of static vlan table (16 entries) if 802.1q vlan mode is enabled, ksz8993m will assign a vi d to every ingress packet. if the packet is untagged or tagged with a null vid, the packet is assigned with the default port vid of the ingress port. if the packet is tagged with non null vid, the vid in the tag will be used. the lookup process will start from the vlan table lookup. if the vid is not valid, the packet will be dro pped and no address learning will take place. if the vid is valid, the fid is retrieved. the fid+da and fid+sa look ups are performed. the fid+da lookup determines the forwarding ports. if fid+da fails, the packet will be broadcast to all the memb ers (excluding the ingress port) of the vlan. if fid+sa fails, t he fid+sa will be learned. examples: 1. vlan table read (read the 3 rd entry) write to reg. 110 with 0x14 (read vlan table selected) write to reg. 111 with 0x02 (trigger the read operation) then read reg. 118 (vlan table bits 19-16) read reg. 119 (vlan table bits 15-8) read reg. 120 (vlan table bits 7-0) 2. vlan table write (write the 7 th entry) write to reg. 118 (vlan table bits 19-16) write to reg. 119 (vlan table bits 15-8) write to reg. 120 (vlan table bits 7-0) write to reg. 110 with 0x04 (write vlan table selected) write to reg. 111 with 0x06 (trigger the write operation) dynamic mac address table this table is read only. the table contents are maintained by ksz8993m only. bit name r/w description default 71 data not ready ro = 1, entry is not ready, retr y until this bit is set to 0 = 0, entry is ready 70-67 reserved ro reserved table 14. format of dynamic mac address table (1k entries) downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 70 m9999-020606 bit name r/w description default 66 mac empty ro = 1, there is no valid entry in the table = 0, there are valid entries in the table 1 65-56 no of valid entries ro indicates how many valid entries in the table 0x3ff means 1 k entries 0x001 means 2 entries 0x000 and bit 66 = 0 means 1 entry 0x000 and bit 66 = 1 means 0 entry 00_0000_0000 55-54 time stamp ro 2 bits counter for internal aging 53-52 source port ro the source port where fid+mac is learned 00, port 1 01, port 2 10, port 3 00 51-48 fid ro filter id 0x0 47-0 mac address ro 48 bits mac address 0x0000_0000_0000 table 14. format of dynamic mac address table (1k entries) (continued) example: dynamic mac address table read (read the 1 st entry and retrieve the mac table size) write to reg. 110 with 0x18 (read dynamic table selected) write to reg. 111 with 0x00 (trigger the read operation) then read reg. 112 (71-64) // if bit 71 = 1, restart (reread) from this register read reg. 113 (63-56) read reg. 114 (55-48) read reg. 115 (47-40) read reg. 116 (39-32) read reg. 117 (31-24) read reg. 118 (23-16) read reg. 119 (15-8) read reg. 120 (7-0) mib (management information base) counters the ksz8993m provides 34 mib counters per port. these counters are used to monitor the port activity for network management. the mib counters have two format gr oups: per port and all port dropped packet. bit name r/w description default 31 reserve ro reserve 0 30 count valid ro = 1, counter value is valid = 0, counter value is not valid 0 29-0 counter values ro counter value 0 table 15. format of per port mib counters per port mib counters are read using indirect memory access. the base address offs ets and address ranges for all three ports are: port 1, base is 0x00 and range is (0x00-0x1f) port 2, base is 0x20 and range is (0x20-0x3f) port 3, base is 0x40 and range is (0x40-0x5f) downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 71 m9999-020606 port 1s per port mib counters indirect memo ry offsets are shown in the following table. offset counter name description 0x0 rxloprioritybyte rx lo-priority (def ault) octet count including bad packets 0x1 rxhiprioritybyte rx hi-priority octet count including bad packets 0x2 rxundersizepkt rx undersize packets w/ good crc 0x3 rxfragments rx fragment packets w/ bad crc, symbol errors or alignment errors 0x4 rxoversize rx oversize packets w/ good crc (max: 1536 or 1522 bytes) 0x5 rxjabbers rx packets longer than 1522 bytes w/ either crc errors, alignment errors, or symbol errors (depends on max packet size setting) 0x6 rxsymbolerror rx packets w/ invalid data symbol and legal packet size. 0x7 rxcrcerror rx packets within (64,1522) bytes w/ an integral number of bytes and a bad crc (upper limit depends on max packet size setting) 0x8 rxalignmenterror rx packets within (64,1522) bytes w/ a non-integral number of bytes and a bad crc (upper limit depends on max packet size setting) 0x9 rxcontrol8808pkts number of mac control fram es received by a port with 88-08h in ethertype field 0xa rxpausepkts number of pause frames received by a port. pause frame is qualified with ethertype (88-08h), da, control opcode (00-01), data length (64b min), and a valid crc 0xb rxbroadcast rx good broadcast packets (not including error broadcast packets or valid multicast packets) 0xc rxmulticast rx good multicast packets (not including mac control frames, error multicast packets or valid broadcast packets) 0xd rxunicast rx good unicast packets 0xe rx64octets total rx packets (bad packets included) that were 64 octets in length 0xf rx65to127octets total rx packets (bad packets included) that are between 65 and 127 octets in length 0x10 rx128to255octets total rx packets (bad packets included) that are between 128 and 255 octets in length 0x11 rx256to511octets total rx packets (bad packets included) that are between 256 and 511 octets in length 0x12 rx512to1023octets total rx packets (bad packets included) that are between 512 and 1023 octets in length 0x13 rx1024to1522octets total rx packets (bad packets included) that are between 1024 and 1522 octets in length (upper limit depends on max packet size setting) 0x14 txloprioritybyte tx lo-priority good octet count, including pause packets 0x15 txhiprioritybyte tx hi-priority good octet count, including pause packets 0x16 txlatecollision the number of times a collision is detected later than 512 bit-times into the tx of a packet 0x17 txpausepkts number of pause frames transmitted by a port 0x18 txbroadcastpkts tx good broadcast packets (not incl uding error broadcast or valid multicast packets) 0x19 txmulticastpkts tx good multicast packets (not including e rror multicast packets or valid broadcast packets) 0x1a txunicastpkts tx good unicast packets table 16. port 1s per port mib counters indirect memory offsets downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 72 m9999-020606 offset counter name description 0x1b txdeferred tx packets by a port for which the 1st tx attempt is delayed due to the busy medium 0x1c txtotalcollision tx total collision, half duplex only 0x1d txexcessivecollision a count of frames for which tx fails due to excessive collisions 0x1e txsinglecollision successfully tx frames on a port for which tx is inhibited by exactly one collision 0x1f txmultiplecollision successfully tx frames on a port for which tx is inhibited by more than one collision table 17. port 1s per port mib counters indirect memory offsets bit name r/w description default 30-16 reserved n/a reserved n/a 15-0 counter values ro counter value 0 table 18. format of all port dropped packet mib counters all port dropped packet mib counters are read using indirect memory acce ss. the address offsets for these counters are shown in the following table: offset counter name description 0x100 port1 tx drop packets tx packets dropped due to lack of resources 0x101 port2 tx drop packets tx packets dropped due to lack of resources 0x102 port3 tx drop packets tx packets dropped due to lack of resources 0x103 port1 rx drop packets rx packets dropped due to lack of resources 0x104 port2 rx drop packets rx packets dropped due to lack of resources 0x105 port3 rx drop packets rx packets dropped due to lack of resources table 19. all port dropped packet mib counters indirect memory offsets examples: 1. mib counter read (read port 1 rx64octets counter) write to reg. 110 with 0x1c (read mib counters selected) write to reg. 111 with 0x0e (trigger the read operation) then read reg. 117 (counter value 30-24) // if bit 30 = 0, restart (reread) from this register read reg. 118 (counter value 23-16) read reg. 119 (counter value 15-8) read reg. 120 (counter value 7-0) 2. mib counter read (read port 2 rx64octets counter) write to reg. 110 with 0x1c (read mib counter selected) write to reg. 111 with 0x2e (trigger the read operation) downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 73 m9999-020606 then, read reg. 117 (counter value 30-24) // if bit 30 = 0, restart (reread) from this register read reg. 118 (counter value 23-16) read reg. 119 (counter value 15-8) read reg. 120 (counter value 7-0) 3. mib counter read (read p ort1 tx drop packets counter) write to reg. 110 with 0x1d (read mib counter selected) write to reg. 111 with 0x00 (trigger the read operation) then read reg. 119 (counter value 15-8) read reg. 120 (counter value 7-0) additional information both per port and all port dropped packet mib counte rs do not indicate overflow. the application must keep track of overflow conditions for these counters. all port dropped packet mib counters do not indicate if count is valid. the application must keep track of valid conditions for these counters. to read out all the counters, the best performance over the spi bus is (160+3)*8*200 = 260ms, where there are 160 registers, 3 overheads, 8 clocks per access, at 5mhz. in the heaviest condition, the counters will overflow in 2 minutes. it is recommended that the software read a ll the counters at least every 30 seconds. a high performance spi master is also recommended to prevent counters overflow. per port mib counters are designed as read clear. that is, these counters will be cleared after they are read. all port dropped packet mib counters ar e not cleared after they are read. downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 74 m9999-020606 absolute maximum ratings (1) description pins value supply storage n/a -55 c to 150 c supply voltage v dda , v ddap , v ddc v ddatx , v ddarx , v ddio C 0.5v to 2.4v C0.5v to 4.0v input voltage (all inputs) all inputs C0.5v to 4.0v output voltage (all outputs all outputs C0.5v to 4.0v lead temperature (solder ing, 10 sec) n/a storage temperature (t s ) n/a -55 c to 150 c note: 1. exceeding the absolute maximu m rating may damage the device. stresses greater than those listed in the table above ma y cause permanent damage to the device. operation of the device at these or any other conditions above those specified in the oper ating sections of this specification is not implied. maximum conditions for extended periods may a ffect reliability. unused inputs must always be tied to an appropriate logic voltage level. operating ratings (1) parameter symbol min typ max supply voltages v dda ,v ddap ,v ddc v ddatx ,v ddarx , v ddio 1.710v 3.135v 1.8v 3.3v 1.890v 3.465v ambient operating temperature (m, ml) t a 0 c 70 c ambient operating temperature (mi, mli) t a -40 c 85 c maximum junction temperature t j 125 c thermal resistance junction to ambient (2) ja 32 c/w notes: 1. the device is not guaranteed to functi on outside its operating rating. unused inputs must always be tied to an appropriate l ogic voltage level (ground to v dd ). 2. no (hs) heat spreader in this package. downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 75 m9999-020606 electrical characteristics (1) v in = xx; r l =xx; t a = 25c, bold values indicate C40c< t a < +85c; unless noted. parameter symbol condition min typ max supply current (including tx output driver current, ksz8993m device only) 100base-tx operation (all ports@100% utilization) 100base-tx (analog core + pll + digital core) i ddc vdda, vddap, vddc = 1.8v 92ma 100base-tx (transceiver + digital i/o) i ddxio vddatx, vddarx, vddio = 3.3v 33ma 10base-t operation (all ports@100% utilization) 10base-t (analog core + pll + digital core) i ddc vdda, vddap, vddc = 1.8v 66ma 10base-t (transceiver + digital i/o) i ddxio vddatx, vddarx, vddio = 3.3v 35ma ttl inputs input high voltage v ih 2.0v input low voltage v il 0.8v input current i in v in = gnd ~ vddio -10 a 10 a ttl outputs output high voltage v oh i oh = -8 ma 2.4v output low voltage v ol i ol = 8 ma 0.4v output tri-state leakage |i oz | 10 a 100base-tx transmit (measured differentially after 1:1 transformer) peak differential output voltage v o 100 ? termination on the differential output. 0.95v 1.05v output voltage imbalance v imb 100 ? termination on the differential output 2 % rise/fall time t r /t f 3ns 5ns rise/fall time imbalance 0ns 0.5ns 100base-tx transmit (measured differentially after 1:1 transformer) duty cycle distortion + 0.5ns overshoot 5 % reference voltage of iset v set 0.5v output jitters peak-to-peak 0.7ns 1.4ns note: 1. specification for packaged product only. downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 76 m9999-020606 electrical character istics (continued) (1) parameter symbol condition min typ max 10baset receive squelch threshold v sq 5mhz square wave 400mv 10baset transmit (measured differentially after 1:1 transformer) vddatx = 3.3v only peak differential output voltage v p 100 ? termination on the differential output. 2.3v jitters added 100 ? termination on the differential output. + 3.5ns rise/fall time 25ns note: 1. specification for packaged product only. downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 77 m9999-020606 timing specifications eeprom timing figure 13. eeprom interf ace input timing diagram figure 14. eeprom interface output timing diagram timing parameter description min typ max unit t cyc1 clock cycle 16384 ns t s1 setup time 20 ns t h1 hold time 20 ns t ov1 output valid 4096 4112 4128 ns table 20. eeprom ti ming parameters downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 78 m9999-020606 sni timing figure 15. sni input timing diagram figure 16. sni output timing diagram timing parameter description min typ max unit t cyc2 clock cycle 100 ns t s2 setup time 10 ns t h2 hold time 0 ns t ov2 output valid 0 3 6 ns table 21. sni timing parameters downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 79 m9999-020606 mii timing mac mode mii timing figure 17. mac-mode mii timing C data received from mii figure 18. mac-mode mii timing C data input to mii timing parameter description min typ max unit t cyc3 (100base-t) clock cycle 100base-t 40 ns tcyc3 (10base-t) clock cycle 10base-t 400 ns t s3 setup time 10 ns t h3 hold time 10 ns t ov3 output valid 0 25 ns table 22. mac-mode mii timing parameters downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 80 m9999-020606 phy-mode mii timing figure 19. phy-mode mii timing C data received from mii figure 20. phy-mode mii timing C data input to mii timing parameter description min typ max unit tcyc4 (100base-t) clock cycle 100base-t 40 ns tcyc4 (10base-t) clock cycle 10base-t 400 ns ts4 setup time 10 ns th4 hold time 10 ns tov4 output valid 0 25 ns table 23. phy-mode mii timing parameters downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 81 m9999-020606 spi timing input timing figure 21. spi input timing timing parameter description min max units fc clock frequency 5 mhz tchsl spis_n inactive hold time 90 ns tslch spis_n active setup time 90 ns tchsh spis_n active old time 90 ns tshch spis_n inactive setup time 90 ns tshsl spis_n deselect time 100 ns tdvch data input setup time 20 ns tchdx data input hold time 30 ns tclch clock rise time 1 us tchcl clock fall time 1 us tdldh data input rise time 1 us tdhdl data input fall time 1 us table 24. spi input timing parameters downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 82 m9999-020606 output timing figure 22. spi output timing timing parameter description min max units fc clock frequency 5 mhz tclqx spiq hold time 0 0 ns tclqv clock low to spiq valid 60 ns tch clock high time 90 ns tcl clock low time 90 tqlqh spiq rise time 50 ns tqhql spiq fall time 50 ns tshqz spiq disable time 100 ns table 25. spi output timing parameters downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 83 m9999-020606 reset timing as long as the stable supply voltages to reset high ti ming (minimum of10ms) are met, there is no power sequencing requirement for the ksz8993m supply voltages (1.8v, 3.3). it is recommended to wait 100sec after the de-asser tion of reset before starting programming on the managed interface. the reset timing requirement is summarized in the following figure and table. figure 23. reset timing parameter description min max units t sr stable supply voltages to reset high 10 ms t cs configuration setup time 50 ns t ch configuration hold time 50 ns t rc reset to strap-in pin output 50 us table 26. reset timing parameters reset circuit diagram micrel recommends the following discrete reset circuit as shown in figure 24 when powering up the ksz8893m/ml/mi device. for the applicat ion where the reset circuit signal comes from another device (e.g., cpu, fpga, etc), we recommend the reset circuit as shown in figure 25. downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 84 m9999-020606 figure 24. recommended reset circuit figure 25. recommended circuit for interfacing with cpu/fpga reset at power-on-reset, r, c, and d1 provide the necessary ramp rise time to reset the micrel device. the reset out from cpu/fpga provides warm reset after power up. it is also recommended to power up the vdd core voltage earlier than vddio voltage. at worst case, the both vdd core and vddio voltages should come up at the same time. downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 85 m9999-020606 selection of isolation transformers a 1:1 isolation transformer is required at the line interfac e. an isolation transformer with integrated common-mode choke is recommended for exceeding fcc requirements. the following table gives recommended transformer characteristics. parameter value test condition turns ratio 1 ct : 1 ct open-circuit inductance (min.) 350 h 100mv, 100khz, 8ma leakage inductance (max.) 0.4 h 1mhz (min.) inter-winding capacitance (max.) 12pf d.c. resistance (max.) 0.9 ? insertion loss (max.) 1.0db 0mhz C 65mhz hipot (min.) 1500vrms table 27. transformer selection criteria magnetic manufacturer part number auto mdi-x number of port bel fuse s558-5999-u7 yes 1 bel fuse si-46001 yes 1 bel fuse si-50170 yes 1 delta lf8505 yes 1 lankom lf-h41s yes 1 pulse h1102 yes 1 pulse (low cost) h1260 yes 1 transpower hb726 yes 1 ycl lf-h41s yes 1 table 28. qualified single port magnetics selection of reference crystal chacteristics value units frequency 25.00000 mhz frequency tolerance (max) 50 ppm load capacitance (max) 20 pf series resistance 25 ? table 29. typical reference crystal characteristics downloaded from: http:///
micrel, inc. ksz8993m/ml october 2008 86 m9999-020606 package information 128-pin pqfp package micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel: +1 (408) 944-0800 fax: +1 (408) 474 1000 web: http:/www.micrel.com the information furnished by micrel in this data sheet is belie ved to be accurate and reliable. however, no responsibility is a ssumed by micrel for its use. micrel reserves the right to change circuitry and specificati ons at any time without notification to the customer. micrel products are not designed or authori zed for use as components in life support app liances, devices or systems where malfu nction of a product can reasonably be expected to result in personal injury. li fe support devices or systems are devices or systems that (a ) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to r esult in a significant injury to the user. a purchaser s use or sale of micrel products for us e in life support appliances, devices or sys tems is a purchasers own risk and purchaser agrees to fully indemnify micrel for any damages resulting from such use or sale. ? 2003 micrel, incorporated. downloaded from: http:///

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